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INTEGRATED CIRCUITS
DEVICE SPECIFICATION
TDA884X/5X-N2 series I2C-bus controlled PAL/NTSC/SECAM TV processors
Tentative Device Specification December 16, 1997 Previous version: April 24, 1997
Philips Semiconductors
Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
FEATURES The following features are available in all IC's: * Multi-standard vision IF circuit with an alignment-free PLL demodulator without external components * Alignment-free multi-standard FM sound demodulator (4.5 MHz to 6.5 MHz) * Audio switch * Flexible source selection with CVBS switch and Y(CVBS)/C input so that a comb filter can be applied * Integrated chrominance trap circuit * Integrated luminance delay line * Asymmetrical peaking in the luminance channel with a (defeatable) noise coring function * Black stretching of non-standard CVBS or luminance signals * Integrated chroma band-pass filter with switchable centre frequency * Dynamic skin tone control circuit * Blue stretch circuit which offsets colours near white towards blue * RGB control circuit with "Continuous Cathode Calibration" and white point adjustment * Possibility to insert a "blue back" option when no video signal is available * Horizontal synchronization with two control loops and alignment-free horizontal oscillator * Vertical count-down circuit * Vertical driver optimised for DC-coupled vertical output stages * I2C-bus control of various functions The detailed differences between the various IC's are given in the table on page 3.
TDA884X/5X-N2 series
GENERAL DESCRIPTION The various versions of the TDA 884X/5X series are I2C-bus controlled single chip TV processors which are intended to be applied in PAL, NTSC, PAL/NTSC and multi-standard television receivers. The N2 version is pin and application compatible with the N1 version, however, a new feature has been added which makes the N2 more attractive. The IF PLL demodulator has been replaced by an alignment-free IF PLL demodulator with internal VCO (no tuned circuit required). The setting of the various frequencies (33.4, 33.9, 38, 38.9, 45,75 and 58.75 MHz) can be made via the I2C-bus. Because of this difference the N2 version is compatible with the N1, however, N1 devices cannot be used in an optimised N2 application. Functionally the IC series is split up is 3 categories, viz: * Versions intended to be used in economy TV receivers with all basic functions (envelope: S-DIP 56 and QFP 64) * Versions with additional features like E-W geometry control, H-V zoom function and YUV interface which are intended for TV receivers with 110 picture tubes (envelope: S-DIP 56) * Versions which have in addition a second RGB input with saturation control and a second CVBS output (envelope: QFP 64) The various type numbers are given in the table below.
SURVEY OF IC TYPES ENVELOPE TV receiver category PAL only PAL/NTSC PAL/SECAM/NTSC NTSC only December 16, 1997 Economy TDA 8840 TDA 8841 TDA 8842 TDA 8846/46A TDA 8843 TDA 8844 TDA 8847 2 S-DIP 56 Mid/High end Economy TDA 8840H TDA 8841H TDA 8842H TDA 8854H TDA 8857H QFP 64 Mid/High end
Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
TDA884X/5X-N2 series
FUNCTIONAL DIFFERENCES BETWEEN THE VARIOUS IC VERSIONS IC VERSION (TDA) Automatic Volume Limiting PAL decoder SECAM decoder NTSC decoder Colour matrix PAL/NTSC(Japan) Colour matrix NTSC Japan/USA YUV interface Base-band delay line for PAL and SECAM or chroma comb filter for NTSC Adjustable luminance delay time Horizontal geometry Horizontal and vertical zoom Vertical scroll 2nd CVBS output X X X X X 8840 X X 8841 X X 8842 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 8846 X 8846A X X X X X X X X X X X X X X X X X X X X X X X X X X X X 8843 8844 8847 8854H 8857H
December 16, 1997
3
Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
QUICK REFERENCE DATA SYMBOL Supply VP IP Input voltages ViVIFrms) ViSIF(rms) ViAUDIO(rms) ViCVBS(p-p) ViCHROMA(p-p) ViRGB(p-p) Output signals VoCVBS(p-p) IoTUNER VoVIDSW(p-p) VoB-Y(p-p) VoR-Y(p-p) VoY(p-p) VoRGB(p-p) IoHOR IoVERT IoEW demodulated CVBS output (peak-to-peak value) tuner AGC output current range CVBS1/CVBS2 output voltage of video switch (peak-to-peak value) -(R-Y) output/input voltage (peak-to-peak value) -(B-Y) output/input voltage (peak-to-peak value) Y output/input voltage (peak-to-peak value) RGB output signal amplitudes (peak-to-peak value) horizontal output current vertical output current (peak-to-peak value) EW drive output current - 0 - - - - - 10 - video IF amplifier sensitivity (RMS value) sound IF amplifier sensitivity (RMS value) external audio input (RMS value) external CVBS/Y input (peak-to-peak value) external chroma input voltage (burst amplitude) (peak-to-peak value) RGB inputs (peak-to-peak value) - - - - - - supply voltage supply current - - PARAMETER
TDA884X/5X-N2 series
MIN.
TYP. - - - - - - - - - 5 - - - - - - - -
MAX.
UNIT
8.0 110
V mA V mV mV V V V
35 1.0 350 1.0 0.3 0.7
2.2 - 2.0/1.0 1.05 1.33 1.4 2.0 - 1 -
V mA V V V V V mA mA mA
1.2
December 16, 1997
4
SCL SDA +8V H-DRIVE
TUNER
CVBS IN
CVBS1 OUT
TDA884X/5X-N2 series
Tentative Device Specification
Fig.1 BLOCK DIAGRAM "ECONOMY VERSIONS" (S-DIP 56 ENVELOPE)
Chr
CVBS/Y
December 16, 1997
53 TOP I2C-BUS SYNC SEP. 2nd LOOP HOR.OUT 50 46 VERT. SYNC CONTROL DAC's SEPARATOR WHITE P CHROMA TRAP + BANDPASS REF SW CVBS-Y/C SWITCH TUNING FILTER RGB CONTROL BLUE STRETCH OUTPUT BRI CONTR 21 20 19 R G B GEOMETRY H/V DIVIDER 47 52 51 VERTICAL V-DRIVE EHT + 1st LOOP VCO + CONTROL TRANSCEIVER POL 7 8 43 39 14 44 12 37 9 42 41 40 MUTE CONTINUOUS CATHODE CALIBRATION
BLOCK DIAGRAMS
54
Philips Semiconductors
AGC FOR IF
IF-IN
48 VIF AMPLIFIER + PLL DEMOD 49 +CALIBRATION
+ TUNER
5
AFC
VIDEO
AMPLIFIER
AFC
IDENT
VIDEO IDENT
VIDEO MUTE
AUDIO OUT
15 55
I2C-bus controlled PAL/NTSC/SECAM TV processors
5
LUMA DELAY PEAKING CORING HUE REF SW BASE-BAND DELAY LINE CVBS SWITCH PAL/NTSC SECAM DECODER 36 35 34 16 33 13 17 38 10 11 FSC
AUDIO IN
2
AVL +
PRE-AMP.
45
SWITCH + VOLUME
+ MUTE
22 BEAM CURR 18 BLACK CURR 23 R1 BLACK STRETCH 24 G1 25 B1 RGB MATRIX 26 BL1 RGB-1 INPUT SAT
56
VOL
SW
1
LIMITER
PLL DEMOD.
CD MATRIX SAT. CONTROL SKIN TINT
6
SOUND BANDPASS
SOUND TRAP
SCL SDA +8V H-DRIVE
TUNER
CVBS IN
CVBS1 OUT
TDA884X/5X-N2 series
Tentative Device Specification
Fig.2 BLOCK DIAGRAM "MID/HIGH-END VERSIONS" (S-DIP 56 ENVELOPE)
Chr
CVBS/Y
December 16, 1997
53 TOP I2C-BUS SYNC SEP. 2nd LOOP EW-GEOMETRY 50 46 VIDEO CONTROL DAC's SEPARATOR WHITE P CHROMA TRAP + BANDPASS REF SW PRE-AMP. CVBS-Y/C SWITCH HUE REF SW CVBS SWITCH + MUTE TUNING FILTER GEOMETRY H/V DIVIDER 47 52 51 VERT. SYNC VERTICAL V-DRIVE EHT HOR.OUT + 1st LOOP VCO + CONTROL 45 TRANSCEIVER POL EW 7 8 43 39 14 44 12 37 9 42 41 40 MUTE BRI CONTR R 21 20 19 22 G B BEAM CURR RGB CONTROL BLUE STRETCH OUTPUT CONTINUOUS CATHODE CALIBRATION
54
Philips Semiconductors
AGC FOR IF
IF-IN
48 VIF AMPLIFIER + PLL DEMOD 49 +CALIBRATION
+ TUNER
5
AFC
AMPLIFIER
AFC
IDENT
VIDEO IDENT
VIDEO MUTE
AUDIO OUT
15 55
I2C-bus controlled PAL/NTSC/SECAM TV processors
6
LUMA DELAY PEAKING CORING SAT BASE-BAND DELAY LINE PAL/NTSC SECAM DECODER 36 35 34 16 33 13 17 38 10 11 28 29 30 SOUND TRAP FSC
AUDIO IN
2
SWITCH +
VOLUME
18 BLACK CURR 23 R1 BLACK STRETCH 24 G1 25 B1 RGB MATRIX 26 BL1 RGB-1 INPUT
56
VOL
SW
1
LIMITER
PLL DEMOD.
CD MATRIX SAT. CONTROL SKIN TINT 32 V 31 U 27 Y
6
SOUND BANDPASS
SCL SDA +8V H-DRIVE
TUNER
CVBS IN
CVBS1 OUT
CVBS2 OUT
TDA884X/5X-N2 series
Tentative Device Specification
Fig.3 BLOCK DIAGRAM "MID/HIGH-END VERSIONS" (QFP-64 ENVELOPE)
Chr CVBS/Y
December 16, 1997
6 17 55 SYNC SEP. 2nd LOOP EW-GEOMETRY 3 63 VERT. SYNC CONTROL DAC's SEPARATOR WHITE P CHROMA TRAP + BANDPASS REF SW CVBS-Y/C SWITCH HUE REF BASE-BAND DELAY LINE TUNING FILTER GEOMETRY H/V DIVIDER 64 4 5 VERTICAL V-DRIVE EHT HOR.OUT + 1st LOOP VCO + CONTROL 62 EW TOP I2C-BUS TRANSCEIVER POL 18 59 25 58 60/61 22/23 53 19 57 56 MUTE BRI CONTR 33 32 31 R G B RGB CONTROL BLUE STRETCH OUTPUT CONTINUOUS CATHODE CALIBRATION
7
Philips Semiconductors
1
IF-IN
2
VIF AMPLIFIER + PLL DEMOD
AGC FOR IF
+CALIBRATION
+ TUNER
15
AFC
VIDEO
AMPLIFIER
AFC
IDENT
VIDEO IDENT
VIDEO MUTE
AUDIO OUT 27
8
I2C-bus controlled PAL/NTSC/SECAM TV processors
7
LUMA DELAY PEAKING CORING SW CVBS SWITCH PAL/NTSC SECAM DECODER 52 51 50 28 49 RGB-2 INPUT RGB/YUV MATRIX 41 24 29 54 26 20 21 FSC
AUDIO IN
11
SWITCH +
PRE-AMP.
VOLUME
+ MUTE
34 BEAM CURR 30 BLACK CURR 35 R1 BLACK STRETCH 36 G1 37 B1 RGB MATRIX 38 BL1 RGB-1 INPUT SAT
9
VOL
SW
10
LIMITER
PLL DEMOD.
CD MATRIX SAT. CONTROL SKIN TINT 42 43 44 40 46 48 V 45 R2 G2 B2 BL2 47 U 39 Y
16
SOUND BANDPASS
SOUND TRAP
Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
PINNING PIN SYMBOL SDIP56 SNDIF AUDIOEXT NC NC PLLLF IFVO SCL SDA DECBG CHROMA CVBS/Y VP1 CVBSINT GND1 AUDIOOUT SECPLL CVBSEXT BLKIN BO GO RO BCLIN RI GI BI RGBIN LUMIN LUMOUT BYO RYO BYI RYI REFO XTAL1 XTAL2 DET VP2 CVBS1O 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 QFP64 10 11 13 14 15 16 17 18 19 20 21 22 24 25 27 28 29 30 31 32 33 34 35 36 37 38 39 40 45 46 47 48 49 50 51 52 53 54 Sound IF input External audio input not connected not connected IF-PLL loop filter IF video output serial clock input serial data input/output bandgap decoupling chrominance input (S-VHS) external CVBS/Y input main supply voltage 1 (+8 V) internal CVBS input ground 1 audio output SECAM PLL decoupling external CVBS input black-current input blue output green output red output
TDA884X/5X-N2 series
DESCRIPTION
beam current limiter input/V-guard input red input for insertion green input for insertion blue input for insertion RGB insertion input luminance input luminance output (B-Y) signal output (R-Y) signal output (B-Y) signal input (R-Y) signal input subcarrier reference output 3.58 MHz crystal connection 4.43/3.58 MHz crystal connection loop filter phase detector 2nd supply voltage 1(+8 V) CVBS-1 output
December 16, 1997
8
Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
PIN SYMBOL SDIP56 DECDIG HOUT FBISO PH2LF PH1LF GND2 EWD VDRB VDRA IFIN1 IFIN2 EHTO VSC Iref DECAGC AGCOUT AUDEEM DECSDEM n.c. VP3 CVBS2O RI2 GI2. BI2 RGBIN2 GND3 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 - - - - - - - - QFP64 55 56 57 58 59 60 62 63 64 1 2 3 4 5 6 7 8 9 12 23 26 41 42 43 44 61 Decoupling digital supply horizontal output
TDA884X/5X-N2 series
DESCRIPTION
flyback input/sandcastle output phase-2 filter phase-1 filter ground 2 east-west drive output vertical drive B output vertical drive A output IF input 1 IF input 2 EHT/overvoltage protection input vertical sawtooth capacitor reference current input AGC decoupling capacitor tuner AGC output Audio deemphasis Decoupling sound demodulator not connected Main supply voltage 2 (+8V) CVBS-2 output 2nd R input 2nd G input 2nd B input 2nd RGB insertion input ground 3
The pin numbers mentioned in the rest of this document are referenced to the SDIP56 (SOT400) package. In the TDA 8840/41/42/46/46A the following pins are different: Pin 16 (SECAM PLL decoupling): Not connected in the TDA 8840/41/46/46A Pin 27: Not connected in TDA 8840/41/42 Pin 28: Luminance output in TDA 8840/41/42 Pin 29-32 (U/V interface): Not available in TDA 8840/41/42 Pin 35 (4.43 MHz X-tal): Not connected in the TDA 8846/46A Pin 45 (E-W drive output): AVL capacitor In the TDA 8857H the pins 28 (SECAM PLL decoupling) and 51 (4.43 MHz X-tal) are not connected.
December 16, 1997
9
Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
TDA884X/5X-N2 series
handbook, halfpage
SNDIF AUDEXT NC NC PLLLF IFVO SCL SDA DECBG
1 2 3 4 5 6 7 8 9
56 55 54 53 52 51 50 49 48 47 46 45 44 43
DECSDEM AUDEEM AGCOUT DECAGC IREF VCS EHTO IFIN2 IFIN1 VDRA VDRB EWD GND2 PH1LF PH2LF FBISO HOUT DECDIG CVBS1O VP2 DET XTAL2 XTAL1 REFO RYI BYI RYO BYO
CHROMA 10 CVBS/Y VP1 CVBSINT GND1
11 12 13 14
AUDOUT 15 SECPLL CVBSEXT BLKIN BO GO RO BCLIN RI GI BI RGBIN LUMIN
16 17 18 19 20 21 22 23 24 25 26 27
XXX TDA 884X
42 41 40 39 38 37 36 35 34 33 32 31 30 29
LUMOUT 28
MXXxxx
Fig.4 Pin configuration (SDIP56).
December 16, 1997
10
Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
TDA884X/5X-N2 series
CVBS1O
DECDIG
PH1LF
PH2LF
GND2
VDRA
VRDB
FBISO
GND3
HOUT
EWD
64
63
62
61
60
59
58
57
56
55
54
53
handbook, full pagewidth
52
51 XTAL2 50 XTAL1 49 REFO 48 RYI 47 BYI 46 45
IFIN1 IFIN2 EHTO VCS IREF DECAGC AGCOUT AUDEEM DECSDEM SNDIF AUDIOEXT NC NC NC PLLF IFVO SCL SDA DECBG
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
DET
VP2
RYO BYO
44 RGB2IN 43 B2IN
TDA 885X XXX
42 G2IN 41 R2IN 40 LUMOUT 39 LUMIN 38 RGBIN 37 BI 36 GI 35 RI 34 BCLIN 33 RO
CHROMA 20
21
22
23
24
25
26
27
28
29
30
31
32
MXXxxx
GND1
AUDIOOUT
SECPLL
VP1
CVBS2O
CVBSINT
CVBS/Y
CVBSEXT
VP3
Fig.5 Pin configuration (QFP64).
December 16, 1997
11
BLKIN
BO
GO
Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
FUNCTIONAL DESCRIPTION Vision IF amplifier The IF-amplifier contains 3 ac-coupled control stages with a total gain control range which is higher then 66 dB. The sensitivity of the circuit is comparable with that of modern IF-IC's. The video signal is demodulated by means of an alignment-free PLL carrier regenerator with an internal VCO. This VCO is calibrated by means of a digital control circuit which uses the X-tal frequency of the colour decoder as a reference. The frequency setting for the various standards (33.4, 33.9, 38, 38.9, 45.75 and 58.75 MHz) is realised via the I2C-bus. To get a good performance for phase modulated carrier signals the control speed of the PLL can be increased by means of the FFI bit. The AFC output is generated by the digital control circuit of the IF-PLL demodulator and can be read via the I2C-bus. For fast search tuning systems the window of the AFC can be increased with a factor 3. The setting is realised with the AFW bit. The AFC data is valid only when the horizontal PLL is in lock (SL = 1) Depending on the type the AGC-detector operates on top-sync level (single standard versions) or on top sync and top white- level (multi standard versions). The demodulation polarity is switched via the I2C-bus. The AGC detector time-constant capacitor is connected externally. This mainly because of the flexibility of the application. The time-constant of the AGC system during positive modulation is rather long to avoid visible variations
TDA884X/5X-N2 series
of the signal amplitude. To improve the speed of the AGC system a circuit has been included which detects whether the AGC detector is activated every frame period. When during 3 field periods no action is detected the speed of the system is increased. For signals without peak white information the system switches automatically to a gated black level AGC. Because a black level clamp pulse is required for this way of operation the circuit will only switch to black level AGC in the internal mode. The circuits contain a video identification circuit which is independent of the synchronisation circuit. Therefore search tuning is possible when the display section of the receiver is used as a monitor. However, this ident circuit cannot be made as sensitive as the slower sync ident circuit (SL) and we recommend to use both ident outputs to obtain a reliable search system. The ident output is supplied to the tuning system via the I2C-bus. The input of the identification circuit is connected to pin 13 (S-DIP 56 devices), the "internal" CVBS input (see Fig.6). This has the advantage that the ident circuit can also be made operative when a scrambled signal is received (descrambler connected between pin 6 (IF video output) and pin 13). A second advantage is that the ident circuit can be used when the IF amplifier is not used (e.g. with built-in satellite tuners). The video ident circuit can also be used to identify the selected CBVS or Y/C signal. The switching between the 2 modes can be realised with the VIM bit.
TO LUMA/SYNC PROCESSING IDENT VIM TO CHROMA PROCESSING
+ VIDEO IDENT +
13(24)
17(29)
11(21)
10(20) 38(54)
(26)
CVBS-INT
CVBS-EXT
Y/CVBS-3
C
CVBS-1 OUT
CVBS-2 OUT
Fig.6 CVBS switch and interfacing of video ident December 16, 1997 12
Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
Video switches The circuits have two CVBS inputs (internal and external CVBS) and a Y/C input. When the Y/C input is not required the Y input can be used as third CVBS input. The switch configuration is given in Fig.6. The selection of the various sources is made via the I2C-bus. For the TDA 884X devices the video switch configuration is identical to the switch of the TDA 8374/75 series. So the circuit has one CVBS output (amplitude of 2 VP-P for the TDA 884X series) and the I2C-bus control is similar to that of the TDA 8374/75. For the TDA 885X IC's the video switch circuit has a second output (amplitude of 1 VP-P) which can be set independently of the position of the first output. The input signal for the decoder is also available on the CVBS1-output. Therefore this signal can be used to drive the Teletext decoder. If S-VHS is selected for one of the outputs the luminance and chrominance signals are added so that a CVBS signal is obtained again. Sound circuit The sound bandpass and trap filters have to be connected externally. The filtered intercarrier signal is fed to a limiter circuit and is demodulated by means of a PLL demodulator. This PLL circuit tunes itself automatically to the incoming carrier signal so that no adjustment is required. The volume is controlled via the I2C-bus. The deemphasis capacitor has to be connected externally. The non-controlled audio signal can be obtained from this pin (via a buffer stage). The FM demodulator can be muted via the I2C-bus. This function can be used to switch-off the sound during a channel change so that high output peaks are prevented. The TDA 8840/41/42/46 contain an Automatic Volume Levelling (AVL) circuit which automatically stabilises the audio output signal to a certain level which can be set by the viewer by means of the volume control. This function prevents big audio output fluctuations due to variations of the modulation depth of the transmitter. The AVL function can be activated via the I2C-bus. Synchronisation circuit The sync separator is preceded by a controlled amplifier which adjusts the sync pulse amplitude to a fixed level. These pulses are fed to the slicing stage which is operating at 50% of the amplitude. The separated sync pulses are fed to the first phase detector and to the coincidence detector. This coincidence detector is used to detect December 16, 1997 13
TDA884X/5X-N2 series
whether the line oscillator is synchronised and can also be used for transmitter identification. This circuit can be made less sensitive by means of the STM bit. This mode can be used during search tuning to avoid that the tuning system will stop at very weak input signals. The first PLL has a very high statical steepness so that the phase of the picture is independent of the line frequency. The horizontal output signal is generated by means of an oscillator which is running at twice the line frequency. Its frequency is divided by 2 to lock the first control loop to the incoming signal. The time-constant of the loop can be forced by the I2C-bus (fast or slow). If required the IC can select the time-constant depending on the noise content of the incoming video signal. The free-running frequency of the oscillator is determined by a digital control circuit which is locked to the reference signal of the colour decoder. When the IC is switched-on the horizontal output signal is suppressed and the oscillator is calibrated as soon as all sub-address bytes have been sent. When the frequency of the oscillator is correct the horizontal drive signal is switched-on. To obtain a smooth switching-on and switching-off behaviour of the horizontal output stage the horizontal output frequency is doubled during switch-on and switch-off (slow start/stop). During that time the duty cycle of the output pulse has such a value that maximum safety is obtained for the output stage. To protect the horizontal output transistor the horizontal drive is immediately switched off when a power-on-reset is detected. The drive signal is switched-on again when the normal switch-on procedure is followed, i.e. all sub-address bytes must be sent and after calibration the horizontal drive signal will be released again via the slow start procedure. When the coincidence detector indicates an out-of-lock situation the calibration procedure is repeated. The circuit has a second control loop to generate the drive pulses for the horizontal driver stage. The horizontal output is gated with the flyback pulse so that the horizontal output transistor cannot be switched-on during the flyback time. Via the I2C-bus adjustments can be made of the horizontal and vertical geometry. The vertical sawtooth generator drives the vertical output drive circuit which has a differential output current. For the E-W drive a single ended current output is available. A special feature is the zoom function for both the horizontal and vertical deflection and the vertical scroll function which are available in some versions. When the horizontal scan is reduced to display 4:3 pictures on a 16:9 picture tube an accurate video blanking can be switched on to obtain well defined edges on the screen.
Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
Overvoltage conditions (X-ray protection) can be detected via the EHT tracking pin. When an overvoltage condition is detected the horizontal output drive signal will be switched-off via the slow stop procedure but it is also possible that the drive is not switched-off and that just a protection indication is given in the I2C-bus output byte. The choice is made via the input bit PRD. The IC's have a second protection input on the 2 filter capacitor pin. When this input is activated the drive signal is switched-off immediately and switched-on again via the slow start procedure. For this reason this protection input can be used as "flash protection". The drive pulses for the vertical sawtooth generator are obtained from a vertical countdown circuit. This countdown circuit has various windows depending on the incoming signal (50 Hz or 60 Hz and standard or non standard). The countdown circuit can be forced in various modes by means of the I2C-bus. During the insertion of RGB signals the maximum vertical frequency is increased to 72 Hz so that the circuit can also synchronise on signals with a higher vertical frequency like VGA. To obtain short switching times of the countdown circuit during a channel change the divider can be forced in the search window by means of the NCIN bit. The vertical deflection can be set in the de-interlace mode via the I2C bus. To avoid damage of the picture tube when the vertical deflection fails the guard output current of the TDA 8350/51 can be supplied to the beam current limiting input. When a failure is detected the RGB-outputs are blanked and a bit is set (NDF) in the status byte of the I2C-bus. When no vertical deflection output stage is connected this guard circuit will also blank the output signals. This can be overruled by means of the EVG bit. Chroma and luminance processing The circuits contain a chroma bandpass and trap circuit. The filters are realised by means of gyrator circuits and they are automatically calibrated by comparing the tuning frequency with the X-tal frequency of the decoder. The luminance delay line and the delay for the peaking circuit are also realised by means of gyrator circuits. The centre frequency of the chroma bandpass filter is switchable via the I2C-bus so that the performance can be optimised for "front-end" signals and external CVBS signals. During SECAM reception the centre frequency of the chroma trap is reduced to get a better suppression of the SECAM carrier frequencies. All IC's have a black stretcher circuit which corrects the black level for incoming video signals which have a deviation between the black level and the blanking level (back porch). The timeconstant for the black stretcher is realised internally. December 16, 1997 14
TDA884X/5X-N2 series
The resolution of the peaking control DAC has been increased to 6 bits. All IC's have a defeatable coring function in the peaking circuit. Some of these IC's have a YUV interface (see table on page 2) so that picture improvement IC's like the TDA 9170 (Contrast improvement), TDA 9177 (Sharpness improvement) and TDA 4556/66 (CTI) can be applied. When the CTI IC's are applied it is possible to increase the gain of the luminance channel by means of the GAI bit in subaddress 03 so that the resulting RGB output signals are not affected. Colour decoder Depending on the IC type the colour decoder can decode PAL, PAL/NTSC or PAL/NTSC/SECAM signals. The PAL/NTSC decoder contains an alignment-free X-tal oscillator, a killer circuit and two colour difference demodulators. The 90 phase shift for the reference signal is made internally. The IC's contain an Automatic Colour Limiting (ACL) circuit which is switchable via the I2C-bus and which prevents that oversaturation occurs when signals with a high chroma-to-burst ratio are received. The ACL circuit is designed such that it only reduces the chroma signal and not the burst signal. This has the advantage that the colour sensitivity is not affected by this function. The SECAM decoder contains an auto-calibrating PLL demodulator which has two references, viz: the 4.4 MHz sub-carrier frequency which is obtained from the X-tal oscillator which is used to tune the PLL to the desired free-running frequency and the bandgap reference to obtain the correct absolute value of the output signal. The VCO of the PLL is calibrated during each vertical blanking period, when the IC is in search or SECAM mode. The frequency of the active X-tal is fed to the Fsc output (pin 33) and can be used to tune an external comb filter (e.g. the SAA 4961). The base-band delay line (TDA 4665 function) is integrated in the PAL/SECAM IC's and in the NTSC IC TDA 8846A. In the latter IC it improves the cross colour performance (chroma comb filter). The demodulated colour difference signals are internally supplied to the delay line. The colour difference matrix switches automatically between PAL/SECAM and NTSC, however, it is also possible to fix the matrix in the PAL standard. The "blue stretch" circuit is intended to shift colour near "white" with sufficient contrast values towards more blue to obtain a brighter impression of the picture.
Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
Which colour standard the IC's can decode depends on the external X-tals. The X-tal to be connected to pin 34 must have a frequency of 3.5 MHz (NTSC-M, PAL-M or PAL-N) and pin 35 can handle X-tals with a frequency of 4.4 and 3.5 MHz. Because the X-tal frequency is used to tune the line oscillator the value of the X-tal frequency must be given to the IC via the I2C-bus. It is also possible to use the IC in the so called "Tri-norma" mode for South America. In that case one X-tal must be connected to pin 34 and the other 2 to pin 35. The switching between the 2 latter X-tals must be done externally. This has the consequence that the search loop of the decoder must be controlled by the -computer. To prevent calibration problems of the horizontal oscillator the external switching between the 2 X-tals should be carried out when the oscillator is forced to pin 34. For a reliable calibration of the horizontal oscillator it is very important that the X-tal indication bits (XA and XB) are not corrupted. For this reason the X-tal bits can be read in the output bytes so that the software can check the I2C-bus transmission. Under bad-signal conditions (e.g. VCR-playback in feature mode), it may occur that the colour killer is activated although the colour PLL is still in lock. When this killing action is not wanted it is possible to overrule the colour killer by forcing the colour decoder to the required standard and to activate the FCO-bit (Forced Colour On) in the control-5 subaddress. The IC's contain a so-called "Dynamic skin tone (flesh) control" feature. This function is realised in the YUV domain by detecting the colours near to the skin tone. The correction angle can be controlled via the I2C-bus. RGB output circuit and black-current stabilisation The colour-difference signals are matrixed with the luminance signal to obtain the RGB-signals. The TDA 884X devices have one (linear) RGB input. This RGB signal can be controlled on contrast and brightness (like TDA 8374/75). By means of the IE1 bit the insertion blanking can be switched on or off. Via the IN1 bit it can be read whether the insertion pin has a high level or not. The TDA 885X IC's have an additional RGB input. This RGB signal can be controlled on contrast, saturation and brightness. The insertion blanking of this input can be switched-off by means of the IE2 bit. Via the IN2 bit it can be read whether the insertion pin has a high level or not.
TDA884X/5X-N2 series
The output signal has an amplitude of about 2 volts black-to-white at nominal input signals and nominal settings of the controls. To increase the flexibility of the IC it is possible to insert OSD and/or teletext signals directly at the RGB outputs. This insertion mode is controlled via the insertion input (pin 26 in the S-DIP 56- and pin 38 in the QFP-64 envelope). This blanking action at the RGB outputs has some delay which must be compensated externally. To obtain an accurate biasing of the picture tube a "Continuous Cathode Calibration" circuit has been developed. This function is realised by means of a 2-point black level stabilisation circuit. By inserting 2 test levels for each gun and comparing the resulting cathode currents with 2 different reference currents the influence of the picture tube parameters like the spread in cut-off voltage can be eliminated. This 2-point stabilisation is based on the principle that the ratio between the cathode currents is coupled to the ratio between the drive voltages according to: V dr1 I k1 ------ = ---------- I k2 V dr2 The feedback loop makes the ratio between the cathode currents Ik1 and Ik2 equal to the ratio between the reference currents (which are internally fixed) by changing the (black) level and the amplitude of the RGB output signals via 2 converging loops. The system operates in such a way that the black level of the drive signal is controlled to the cut-off point of the gun so that a very good grey scale tracking is obtained. The accuracy of the adjustment of the black level is just dependent on the ratio of internal currents and these can be made very accurately in integrated circuits. An additional advantage of the 2-point measurement is that the control system makes the absolute value of Ik1 and Ik2 identical to the internal reference currents. Because this adjustment is obtained by means of an adaption of the gain of the RGB control stage this control stabilises the gain of the complete channel (RGB output stage and cathode characteristic). As a result variations in the gain figures during life will be compensated by this 2-point loop.
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15
Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
An important property of the 2-point stabilisation is that the off-set as well as the gain of the RGB path is adjusted by the feedback loop. Hence the maximum drive voltage for the cathode is fixed by the relation between the test pulses, the reference current and the relative gain setting of the 3 channels. This has the consequence that the drive level of the CRT cannot be adjusted by adapting the gain of the RGB output stage. Because different picture tubes may require different drive levels the typical "cathode drive level" amplitude can be adjusted by means of an I2C-bus setting. Dependent on the chosen cathode drive level the typical gain of the RGB output stages can be fixed taking into account the drive capability of the RGB outputs (pins 19 to 21). More details about the design will be given in the application report. The measurement of the "high" and the "low" current of the 2- point stabilisation circuit is carried out in 2 consecutive fields. The leakage current is measured in each field. The maximum allowable leakage current is 100 A When the TV receiver is switched-on the RGB output signals are blanked and the black current loop will try to set the right picture tube bias levels. Via the AST bit a choice can be made between automatic start-up or a start-up via the -processor. In the automatic mode the RGB drive signals are switched-on as soon as the black current loop has been stabilised. In the other mode the BCF bit is set to 0 when the loop is stabilised. The RGB drive can than be switched-on by setting the AST bit to 0. In the latter mode some delay can be introduced between the setting of the BCF bit and the switching of the AST bit so that switch-on effects can be suppressed. It is also possible to start-up the devices with a fixed internal delay (as with the TDA 837X and the TDA884X/5X N1). This mode is activated with the BCO bit. The vertical blanking is adapted to the incoming CVBS signal (50 Hz or 60 Hz). When the flyback time of the vertical output stage is longer than the 60 Hz blanking time the blanking can be increased to the same value as that of the 50 Hz blanking. This can be set by means of the LBM bit.
TDA884X/5X-N2 series
For an easy (manual) adjustment of the Vg2 control voltage the VSD bit is available. When this bit is activated the black current loop is switched-off, a fixed black level is inserted at the RGB outputs and the vertical scan is switched-off so that a horizontal line is displayed on the screen. This line can be used as indicator for the Vg2 adjustment. Because of the different requirements for the optimum cut-off voltage of the picture tube the RGB output level is adjustable when the VSD bit is activated. The control range is 2.5 0.7 V and can be controlled via the brightness control DAC. It is possible to insert a so called "blue back" back-ground level when no video is available. This feature can be activated via the BB bit in the control2 subaddress. I2C-BUS SPECIFICATION The slave address of the IC's is given in Fig.7. The circuit operates up to clock frequencies of 400 kHz.
handbook, halfpage
A6 1
A5 0
A4 0
A3 0
A2 1
A1 0
A0 1
R/W 1/0
MLA743
Fig.7 Slave address (8A).
Start-up procedure Read the status bytes until POR = 0 and send all subaddress bytes. The horizontal output signal is switched-on when the oscillator is calibrated. Each time before the data in the IC is refreshed, the status bytes must be read. If POR = 1, the procedure mentioned above must be carried out to restart the IC. When this procedure is not followed the horizontal frequency may be incorrect after power-up or after a power dip.
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Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
TDA 8840/41/42/46/46A:
TDA884X/5X-N2 series
Valid subaddresses: 00 to 1A (subaddresses 04 to 07 and 17 are not used), subaddress FE is reserved for test purposes. Auto-increment mode available for subaddresses. The bit L'FA is only valid in the TDA 8842, the function of the colour mode bits (CM0-CM2 and CD0-CD2) is dependent on the functional content of the IC. Table 1 Input status bits. FUNCTION Control 0 Control 1 Hue Horizontal shift (HS) Vertical slope (VS) Vertical amplitude (VA) S-correction (SC) Vertical shift (VSH) White point R White point G White point B Peaking Brightness Saturation Contrast AGC take-over Volume control Adjustment IF-PLL Control 2 Control 3 Control 4 Control 5 Table 2 Output status bits. FUNCTION Output status bytes SUBADDRESS (HEX) 00 01 02 DATA BYTE D7 POR NDF N2 D6 FSI IN1 X D5 X X BCF D4 SL IFI IVW D3 XPR AFA ID3 D2 CD2 AFB ID2 D1 CD1 SXA ID1 D0 CD0 SXB ID0 SUBADDRESS (HEX) 00 01 02 03 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 18 19 1A 1B DATA BYTE D7 INA AVL VIM NCIN VID 0 SBL 0 0 MAT 0 RBL IE1 AFW MOD SM IFA OSO HOB 0 0 D6 INB AKB GAI STM LBM EVG PRD 0 0 0 0 COR 0 IFS VSW FAV IFB VSD BPS 0 0 D5 INC DL A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 IFC CB ACL 0 0 D4 BCO STB A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 0 BLS CMB 0 0 D3 FOA POC A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 0 BKS AST DS 0 D2 FOB CM2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 0 0 CL2 DSA 0 D1 XA CM1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 0 0 CL1 FFI 0 D0 XB CM0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 0 BB CL0 EBS FCO
FORF FORS
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Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
TDA 8843/44/47:
TDA884X/5X-N2 series
Valid subaddresses: 00 to 1A, subaddress FE is reserved for test purposes. Auto-increment mode available for subaddresses. The bits L'FA, CM0-CM2 and CD0-CD2 are only available in the TDA 8843/44. Table 3 Input status bits. FUNCTION Control 0 Control 1 Hue Horizontal shift (HS) EW width (EW) EW parabola/width (PW) EW corner parabola (CP) EW trapezium (TC) Vertical slope (VS) Vertical amplitude (VA) S-correction (SC) Vertical shift (VSH) White point R White point G White point B Peaking Brightness Saturation Contrast AGC take-over Volume control Adjustment IF-PLL Vertical zoom (VX) Vertical scroll Control 2 Control 3 Control 4 Control 5 Table 4 Output status bits FUNCTION Output status bytes SUBADDRESS (HEX) 00 01 02 December 16, 1997 DATA BYTE D7 POR NDF N2 18 D6 FSI IN1 X D5 X X BCF D4 SL IFI IVW D3 XPR AFA ID3 D2 CD2 AFB ID2 D1 CD1 SXA ID1 D0 CD0 SXB ID0 SUBADDRESS (HEX) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B DATA BYTE D7 INA HBL VIM 0 0 0 0 NCIN VID HCO SBL 0 0 MAT 0 RBL IE1 AFW MOD SM IFA 0 0 OSO HOB YD3 0 D6 INB AKB GAI 0 0 0 0 STM LBM EVG PRD 0 0 0 0 COR 0 IFS VSW FAV IFB 0 0 VSD BPS YD2 0 D5 INC DL A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 IFC A5 A5 CB ACL YD1 0 D4 BCO STB A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 0 A4 A4 BLS CMB YD0 0 D3 FOA POC A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 0 A3 A3 BKS AST DS 0 D2 FOB CM2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 0 A2 A2 0 CL2 DSA 0 D1 XA CM1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 0 A1 A1 0 CL1 FFI 0 D0 XB CM0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 0 A0 A0 BB CL0 EBS FCO
FORF FORS
Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
TDA 8854/57:
TDA884X/5X-N2 series
Valid subaddresses: 00 to 1A, subaddress FE is reserved for test purposes. Auto-increment mode available for subaddresses. The bits L'FA, CM0-CM2 and CD0-CD2 are only available in the TDA 8854. Table 5 Input status bits. FUNCTION Control 0 Control 1 Hue Horizontal shift (HS) EW width (EW) EW parabola/width (PW) EW corner parabola (CP) EW trapezium (TC) Vertical slope (VS) Vertical amplitude (VA) S-correction (SC) Vertical shift (VSH) White point R White point G White point B Peaking Brightness Saturation Contrast AGC take-over Volume control Adjustment IF-PLL Vertical zoom (VX) Vertical scroll Control 2 Control 3 Control 4 Control 5 Table 6 Output status bits FUNCTION Output status bytes SUBADDRESS (HEX) 00 01 02 DATA BYTE D7 POR NDF N2 D6 FSI IN1 X D5 X IN2 BCF D4 SL IFI IVW D3 XPR AFA ID3 D2 CD2 AFB ID2 D1 CD1 SXA ID1 D0 CD0 SXB ID0 SUBADDRESS (HEX) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B DATA BYTE D7 INA HBL VIM 0 0 0 0 NCIN VID HCO SBL 0 0 MAT 0 RBL IE1 AFW MOD SM IFA 0 0 OSO HOB YD3 0 D6 INB AKB GAI 0 0 0 0 STM LBM EVG PRD 0 0 0 0 COR IE2 IFS VSW FAV IFB 0 0 VSD BPS YD2 0 D5 INC DL A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 IFC A5 A5 CB ACL YD1 0 D4 BCO STB A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 0 A4 A4 BLS CMB YD0 0 D3 FOA POC A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 0 A3 A3 BKS AST DS 0 D2 FOB CM2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 0 A2 A2 CS1 CL2 DSA 0 D1 XA CM1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 0 A1 A1 CS0 CL1 FFI 0 D0 XB CM0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 0 A0 A0 BB CL0 EBS FCO
FORF FORS
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Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
INPUT CONTROL BITS Table 7 INA 0 0 0 0 1 1 Note 1. These modes are intended for comb filter applications. Table 8 BCO 0 1 Table 9 FOA 0 0 1 1 Switch-on behaviour STATUS switch-on of picture without delay switch-on of picture via internal delay Phase 1 (1) time constant FOB 0 1 0 1 normal slow slow/fast fast MODE Source select INB 0 0 1 1 0 1 INC 0 1 0 1 0 0 SELECTED SIGNALS Internal CVBS+ audio External CVBS+ audio Y/C + ext. audio CVBS3 + ext. audio Y/C + int audio, note 1 CVBS1 OUTPUT Int. CVBS Ext. CVBS Y/C(Y+C) CVBS3 Int CVBS Table 13 Stand-by STB 0 1 stand-by normal Table 12 Interlace DL 0 1 interlace
TDA884X/5X-N2 series
STATUS de-interlace
MODE
Y/C + ext audio, note 1 Ext. CVBS Table 14 Synchronization mode POC 0 1 active not active MODE
Table 15 Colour decoder mode CM2 0 0 0 0 1 1 1 1 CM1 0 0 1 1 0 0 1 1 CM0 0 1 0 1 0 1 0 1 DECODER MODE not forced, own intelligence forced X-tal pin 34 PAL/NTSC forced X-tal pin 34 PAL forced X-tal pin 34 NTSC forced X-tal pin 35 PAL/NTSC forced X-tal pin 35 PAL forced X-tal pin 35 NTSC Forced SECAM (X-tal pin 35)
Table 10 Crystal indication Table 16 Auto. Volume Levelling (TDA 8840/1/2/6/6A) XA 0 0 1 1 XB 0 1 0 1 two 3.6 MHz one 3.6 MHz (pin 34) one 4.4 MHz (pin 35) 3.6 MHz (pin 34) and 4.4 MHz (pin 35) CRYSTAL AVL 0 1 not active active MODE
Table 17 RGB blanking mode (TDA 8843/44/47/54/57) HBL MODE normal blanking (horizontal flyback) wide blanking
Table 11 Forced field frequency FORF 0 0 1 1 FORS 0 1 0 1 60 Hz keep last detected field frequency auto (50 Hz when line not in sync) FIELD FREQUENCY auto (60 Hz when line not in sync)
0 1
Table 18 Black current stabilisation AKB 0 1 active not active MODE
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Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
Table 19 Video ident mode VIM 0 1 MODE ident coupled to internal CVBS (pin 13) ident coupled to selected CVBS
TDA884X/5X-N2 series
Table 27 Service blanking SBL 0 1 off on SERVICE BLANKING MODE
Table 20 Gain of luminance channel GAI 0 1 MODE normal gain (V27 = 1 VBL-WH) high gain (V27 = 0.45 VP-P)
Table 28 Overvoltage input mode PRD 0 1 OVERVOLTAGE MODE detection mode protection mode
Table 21 Vertical divider mode NCIN 0 1 VERTICAL DIVIDER MODE normal operation switched to search window
Table 29 PAL-SECAM/NTSC matrix (TDA8841/2/3/4/54) MAT 0 1 PAL matrix MATRIX POSITION adapted to standard
Table 22 Search tuning mode STM 0 1 normal operation reduced sensitivity of video indent circuit MODE
Table 30 NTSC matrix (TDA 8846/46A/47/57) MAT 0 1 USA matrix MATRIX POSITION Japanese matrix
Table 23 Video ident mode VID 0 1 not active VIDEO IDENT MODE 1 loop switched on and off
Table 31 RGB blanking RBL 0 1 not active active RGB BLANKING
Table 24 Long blanking mode LBM 0 1 BLANKING MODE adapted to standard (50 or 60 Hz) fixed in accordance with 50 Hz standard
Table 32 Noise coring (peaking) COR 0 1 off on NOISE CORING
Table 25 EHT tracking mode HCO 0 1 TRACKING MODE EHT tracking only on vertical EHT tracking on vertical and EW
Table 33 Enable fast blanking RGB-1 IE1 0 1 not active active FAST BLANKING
Table 26 Enable vertical guard (RGB blanking) EVG 0 1 active VERTICAL GUARD MODE not active
Table 34 Enable fast blanking RGB-2 (TDA 885X) IE2 0 1 not active active FAST BLANKING
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Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
Table 35 AFC window AFW 0 1 normal enlarged AFC WINDOW
TDA884X/5X-N2 series
Table 42 Switch-off in vertical overscan OSO 0 1 MODE Switch-off undefined Switch-off in vertical overscan
Table 36 IF sensitivity IFS 0 1 normal reduced IF SENSITIVITY
Table 43 Vertical scan disable VSD 0 1 Vertical scan active Vertical scan disabled MODE
Table 37 Modulation standard MOD 0 1 negative positive MODULATION
Table 44 Chroma bandpass centre frequency CB 0 1 FSC 1.1 x FSC CENTRE FREQUENCY
Table 38 Video mute VSW 0 1 normal operation IF-video signal switched off STATE
Table 45 Blue stretch BLS 0 1 off on BLUE STRETCH MODE
Table 39 Sound mute SM 0 1 normal operation sound mute active STATE
Table 46 Black stretch BKS 0 1 off on BLACK STRETCH MODE
Table 40 Fixed audio volume FAV 0 1 MODE normal volume control audio output level fixed
Table 47 2nd CVBS output (TDA 885X) CS1 0 0 1 1 CS0 0 1 0 1 CVBS-2 OUTPUT internal CVBS external CVBS Y/C (Y + C) CVBS-3
Table 41 PLL demodulator frequency adjust IFA 0 0 0 0 1 1 IFB 0 0 1 1 0 1 IFC 0 1 0 1 0 0 IF FREQUENCY 58.75 MHz 45.75 MHz 38.90 MHz 38.00 MHz 33.40 MHz 33.90 MHz
Table 48 Blue back when no video signal is identified BB 0 1 off on BLUE BACK
Table 49 Helper output blanking (PALPLUS) HOB 0 1 not active active OUTPUT BLANKING
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Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
Table 50 Bypass of chroma base-band delay line BPS 0 1 active bypassed 0 0 Table 51 Automatic colour limiting ACL 0 1 not active active COLOUR LIMITING 0 0 1 1 1 Table 52 Enable external comb filter CMB 0 1 disabled enabled COMB FILTER 1 Note 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 DELAY LINE MODE
TDA884X/5X-N2 series
Table 54 Cathode drive level CL2 CL1 CL0 SETTING CATHODE DRIVE AMPLITUDE; NOTE 1 57VBL-WH 63 VBL-WH 70 VBL-WH 77 VBL-WH 84 VBL-WH 91 VBL-WH 99 VBL-WH 107 VBL-WH
1. The given values are valid for the following conditions: - Nominal CVBS input signal - Settings for contrast, WPA and peaking nominal - Black- and blue-stretch switched-off - Gain of output stage such that no clipping occurs - Beam current limiting not active The tolerance on these values is about 3 V. Table 55 Y-delay adjustment; note 1 YD0 to YD3 YD3 YD2 YD1 YD0 Note 1. For an equal delay of the luminance and chrominance signal the delay must be set at a value of 160 ns. This is only valid for a CVBS signal without group delay distortions. Table 56 Dynamic skin control on/off DS 0 1 off on MODE YD3 160 ns + YD2 80 ns + YD1 40 ns + YD0 40 ns Y-DELAY
Table 53 Start-up mode of black current loop; note 1 AST 0 1 Note 1. When the circuit is in the automatic mode the RGB drive is switched-on as soon as the black current loop has stabilised. Under control of the -processor the condition of the black current loop is indicated via the BCF bit. When this bit changes to 0 the RGB drive can be switched-on by setting the AST bit to 0. automatic mode; switch-on under control of -processor MODE
Table 57 Dynamic skin control angle DSA 0 1 ANGLE OF CORRECTION correction angle 123 degrees correction angle 117 degrees
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Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
Table 58 Fast filter IF-PLL FFI 0 1 CONDITION normal time constant increased time constant
TDA884X/5X-N2 series
Table 60 Forced Colour-On FCO 0 1 CONDITION normal colour killer function no colour killer (in forced colour mode only)
Table 59 Extended Blue Stretch EBS 0 1 off on CONDITION
December 16, 1997
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Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
OUTPUT CONTROL BITS Table 61 Power-on-reset POR 0 1 normal power-down MODE
TDA884X/5X-N2 series
Table 68 Output video identification IFI 0 1 VIDEO SIGNAL no video signal identified video signal identified
Table 69 AFC output AFA 0 0 1 1 AFB 0 1 0 1 CONDITION outside window; too low outside window; too high in window; below reference in window; above reference
Table 62 Field frequency indication FSI 0 1 50 Hz 60 Hz FREQUENCY
Table 63 Phase 1 (1) lock indication SL 0 1 not locked locked INDICATION Table 70 X-tal indication SXA 0 0 Table 64 X-ray protection XPR 0 1 OVERVOLTAGE no overvoltage detected overvoltage detected BCF Table 65 Colour decoder mode CD2 0 0 0 0 1 1 1 CD1 0 0 1 1 0 0 1 CD0 0 1 0 1 0 1 0 STANDARD no colour standard identified NTSC with X-tal pin 34 PAL with X-tal pin 35 SECAM NTSC with X-tal pin 35 PAL with X-tal pin 34 spare N2 0 1 N1 version N2 version MASK VERSION 0 1 CONDITION black current loop is stabilised black current loop is not stabilised 1 1 SXB 0 1 0 1 CONDITION two 3.6 MHz X-tals only 3.6 MHz X-tal only 4.4 MHz X-tal 3.6 and 4.4 MHz X-tal
Table 71 Condition black current loop
Table 72 Mask version indication
Table 73 Condition vertical divider IVW STANDARD VIDEO SIGNAL no standard video signal standard video signal (525 or 625 lines)
Table 66 Output vertical guard NDF 0 1 OK failure VERTICAL OUTPUT STAGE
0 1
Table 67 Indication RGB-1/2 (TDA 885X)insertion INX 0 1 RGB INSERTION no (pin 26/38 and/or 44 LOW) yes (pin 26/38 and/or 44HIGH)
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Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
Table 74 IC version indication ID3 0 0 0 0 1 0 0 0 1 1 ID2 0 0 0 0 0 1 1 1 1 1 ID1 0 1 1 0 0 1 1 0 1 0 ID0 1 0 1 0 0 0 1 0 1 0 TDA 8840/40H TDA 8841/41H TDA 8842/42H TDA 8846 TDA 8846A TDA 8843 TDA 8844 TDA 8847 TDA 8854H TDA 8857H IC TYPE
TDA884X/5X-N2 series
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Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VP Tstg Tamb Tsol Tj Ves PARAMETER supply voltage storage temperature operating ambient temperature soldering temperature operating junction temperature electrostatic handling for 5 s CONDITIONS
TDA884X/5X-N2 series
MIN. - -25 0 - -
MAX. 9.0 +150 70 260 150 +2000 +200 V
UNIT C C C C V V
HBM; all pins; notes 1 and 2 -2000 MM; all pins; notes 1 and 3 -200
Notes 1. All pins are protected against ESD by means of internal clamping diodes. 2. Human Body Model (HBM): R = 1.5 k; C = 100 pF. 3. Machine Model (MM): R = 0 ; C = 200 pF. THERMAL CHARACTERISTICS (THERMAL RESISTANCE FROM JUNCTION TO AMBIENT IN FREE AIR) SYMBOL Rth j-a SDIP 56 QFP 64 QUALITY SPECIFICATION In accordance with "SNW-FQ-611E". The number of the quality specification can be found in the "Quality Reference Handbook". The handbook can be ordered using the code 9398 510 63011. Latch-up At an ambient temperature of 70 C nearly all pins meet the following specification: * Itrigger 100 mA or 1.5VDD(max) * Itrigger -100 mA or -0.5VDD(max). Some pins have a slightly lower trigger current. The pin numbers and and the allowable trigger current are given below. Pin 50: Itrigger 70 mA Pin 51: Itrigger 60 mA Pin 52: Itrigger 60 mA ENVELOPE 40 50 VALUE K/W K/W UNIT
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Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
CHARACTERISTICS VP = 8 V; Tamb = 25 C; unless otherwise specified. NUMBER Supplies POWER SUPPLY (PINS 12 AND 37) V.1.1 V.1.2 V.1.3 V.1.4 IF circuit VISION IF AMPLIFIER INPUTS (PINS 48 AND 49) input sensitivity (RMS value) M.1.1 M.1.2 M.1.3 M.1.4 M.1.5 M.1.6 M.1.7 input resistance (differential) input capacitance (differential) gain control range maximum input signal (RMS value) note 1 fi = 38.90 MHz fi = 45.75 MHz fi = 58.75 MHz note 2 note 2 supply voltage supply current pin 12 supply current pin 37 total power dissipation PARAMETER CONDITIONS
TDA884X/5X-N2 series
MIN.
TYP.
MAX.
UNIT
7.2 - - -
8.0 70 60 1040
8.8 - - -
V mA mA mW
10 10 10 - - 64 150
35 35 35 2 3 75 -
100 100 100 - - - -
V V V k pF dB mV
PLL DEMODULATOR (PLL FILTER ON PIN 5); NOTES 3 AND 4 M.2.1 M.2.2 M.2.3 Free-running frequency of VCO Catching range PLL Acquisition time PLL PLL not locked, deviation from nominal setting -500 - - - 2 - +500 - 20 kHz MHz ms
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Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
NUMBER PARAMETER CONDITIONS
TDA884X/5X-N2 series
MIN. - - 1.8 - -
TYP. - -
MAX.
UNIT
VIDEO AMPLIFIER OUTPUT (PIN 6); NOTE 6 M.3.1 M.3.2 M.3.3 M.3.4 M.3.5 top sync level white level difference in amplitude between negative and positive modulation video output impedance internal bias current of NPN emitter follower output transistor maximum source current bandwidth of demodulated output signal differential gain differential phase video non-linearity white spot clamp level noise inverter clamping level noise inverter insertion level (identical to black level) intermodulation M.3.16 M.3.17 M.3.18 M.3.19 signal-to-noise ratio M.3.20 M.3.21 M.3.22 M.3.23 residual carrier signal residual 2nd harmonic of carrier signal yellow blue note 10 note 10 notes 5 and 11 Vo = 0.92 or 1.1 MHz Vo = 2.66 or 3.3 MHz Vo = 0.92 or 1.1 MHz Vo = 2.66 or 3.3 MHz notes 5 and 12 weighted unweighted note 5 note 5 56 49 - - 60 53 5.5 2.5 - - - - dB dB mV mV 60 60 56 60 66 66 62 66 - - - - dB dB dB dB at -3 dB note 8 notes 8 and 5 note 9 zero signal output level negative modulation; note 7 positive modulation; note 7 negative modulation positive modulation 4.2 2.2 1.9 4.4 0 V V V V %
2.0 - 15
M.3.6 M.3.7 M.3.8 M.3.9 M.3.10 M.3.11 M.3.12 M.3.13 M.3.14 M.3.15
- 1.0 - 6 - - - - - -
50 - - 9 2 - - 6.0 1.5 2.7
- - 5 - 5 5 5 - - -
mA mA MHz % deg % V V V
IF AND TUNER AGC; NOTE 13
Timing of IF-AGC with a 2.2 F capacitor (pin 53)
M.4.1 M.4.2 M.4.3 M.4.4 M.4.5 M.4.6 modulated video interference response time to IF input signal amplitude increase of 52 dB response to an IF input signal amplitude decrease of 52 dB allowed leakage current of the AGC capacitor 30% AM for 1 mV to 100 mV; - 0 to 200 Hz (system B/G) positive and negative modulation negative modulation positive modulation negative modulation positive modulation 29 - - - - - - 2 50 100 - - 10 - - - 10 200 % ms ms ms A nA
December 16, 1997
Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
NUMBER PARAMETER CONDITIONS
TDA884X/5X-N2 series
MIN. - 40
TYP.
MAX.
UNIT
Tuner take-over adjustment (via I2C-bus)
M.5.1 M.5.2 minimum starting level for tuner take-over (RMS value) maximum starting level for tuner take-over (RMS value) 0.2 60 0.8 - mV mV
Tuner control output (pin 54)
M.6.1 M.6.2 M.6.3 M.6.4 M.6.5 maximum tuner AGC output voltage output saturation voltage maximum tuner AGC output swing leakage current RF AGC input signal variation for complete tuner control maximum tuner gain; note 2 minimum tuner gain; IO = 2 mA - - 5 - 0.5 - - - - 2 9 300 - 1 4 V mV mA A dB
AFC OUTPUT (VIA I2C-BUS); NOTE 14 M.7.1 M.7.2 M.7.3 AFC resolution window sensitivity window sensitivity in large window mode - - - 2 125 275 - - - bits kHz kHz
VIDEO IDENTIFICATION OUTPUT (VIA I2C-BUS) M.8.1 delay time of identification after the AGC has stabilized on a new transmitter - - 10 ms
Sound circuit DEMODULATOR INPUT; (PIN 1) G.1.1 G.1.2 G.1.3 G.1.4 G.1.5 input limiting for PLL catching range (RMS value) catching range PLL input resistance input capacitance AM rejection note 15 note 2 note 2 VI = 50 mV RMS; note 16 note 15 - 4.2 - - 60 - - - 1 - 8.5 - 66 2 6.8 - 5 - - - - mV MHz k pF dB
DE-EMPHASIS (PIN 55) G.2.1 G.2.2 G.2.3 output signal amplitude (RMS value) output resistance DC output voltage 500 15 3 mV k V
December 16, 1997
30
Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
NUMBER AUDIO OUTPUT (PIN 15) G.3.1 G.3.2 G.3.3 G.3.4 G.3.5 G.3.6 G.3.7 G.3.8 G.3.9 G.3.10 G.3.11 G.3.12 controlled output signal amplitude (RMS value) output resistance DC output voltage total harmonic distortion total harmonic distortion power supply rejection internal signal-to-noise ratio external signal-to-noise ratio output level variation with temperature control range suppression of output signal when mute is active DC shift of the output when mute is active note 17 FAV = 1; note 18 note 5 note 5 + 19 note 5 + 19 note 5 + 20 see also Fig.8 -6 dB; note 15 PARAMETER CONDITIONS
TDA884X/5X-N2 series
MIN.
TYP.
MAX.
UNIT
500 - - - - - - - -
700 500 3.0 0.15 0.15 25 60 80 80 80 50
900 - - 0.5 0.5 - tbf - - 100
mV V % % dB dB dB dB dB dB mV
EXTERNAL AUDIO INPUT; (PIN 2) G.4.1 G.4.2 G.4.3 G.4.4 input signal amplitude (RMS value) input resistance voltage gain difference between input and output crosstalk between internal and external audio signals maximum volume - - - 60 500 25 9 - 2000 - - - mV k dB dB
AUTOMATIC VOLUME LEVELLING (ONLY IN TDA 8840/41/42/46/46A); CAPACITOR CONNECTED TO PIN 45; NOTE 21 G.5.1 G.5.2 G.5.3 G.5.4 G.5.5 G.5.6 gain at maximum boost gain at minimum boost charge (attack) current discharge (decay) current control voltage at maximum boost control voltage at minimum boost - - - - - - 6 -14 1 200 1 5 - - - - - - dB dB mA nA V V
December 16, 1997
31
Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
NUMBER PARAMETER CONDITIONS
TDA884X/5X-N2 series
MIN.
TYP.
MAX.
UNIT
CVBS, Y/C, RGB, CD AND LUMINANCE OUT- AND INPUTS CVBS-Y/C SWITCH, PINS 10, 11, 13, 17 AND 38 (20, 21, 24, 26, 29 AND 54 FOR TDA 885X) S.1.1 S.1.2 S.1.3 S.1.4 S.1.5 S.1.6 S.1.7 S.1.8 S.1.9 S.1.10 CVBS or Y input voltage (peak-to-peak value) CVBS or Y input current suppression of non-selected CVBS input signal chrominance input voltage (burst amplitude) chrominance input impedance output signal amplitude (CVBS1) (peak-to-peak value) black level of CVBS1 output signal amplitude (CVBS2) (peak-to-peak value) black level of CVBS2 output impedance notes 5 and 23 note 2 and 24 note 22 - - 50 - - - - - - - note 25 - 1.0 4 - 0.3 50 2.0 2.1 1.0 3.3 - 0.7 1.4 - - 1.0 - - - - - 250 V A dB V k V V V V V
RGB INPUTS, PINS 23 TO 25 (35 TO 37 AND 41 TO 43 FOR TDA 885X) S.2.1 input signal amplitude for an output signal of 2 V (black-to-white) (peak-to-peak value) input signal amplitude before clipping occurs (peak-to-peak value) difference between black level of internal and external signals at the outputs input currents delay difference for the three channels no clamping; note 2 note 5 0.8
S.2.2
note 5
1.0
-
-
V
S.2.3
-
-
20
mV
S.2.4 S.2.5
- -
0.1 0
1 20
A ns
FAST BLANKING, PIN 26 (38 AND 44 FOR TDA 885X) S.3.1 S.3.2 S.3.3 S.3.4 S.3.5 maximum input pulse delay time from RGB in to RGB out delay difference between insertion to RGB out and RGB in to RGB out input current suppression of internal RGB signals notes 5 and 23; insertion; fi = 0 to 5 MHz 32 input voltage no data insertion data insertion insertion data insertion; note 5 data insertion; note 5 - 0.9 - - - - 0.6 - - - 0.4 - 3.0 60 20 V V V ns ns
S.3.6 S.3.7
- -
- 55
0.2 -
mA dB
December 16, 1997
Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
NUMBER PARAMETER CONDITIONS
TDA884X/5X-N2 series
MIN. - 4
TYP. - -
MAX.
UNIT
FAST BLANKING INPUT (CONTINUED) S.3.8 S.3.9 suppression of external RGB signals notes 5 and 23; no insertion; fi = 0 to 5 MHz 55 - dB V
input voltage to blank the RGB only on pin 26 (pin 38 for the outputs to facilitate `On Screen TDA 885X) Display' signals being applied to the outputs
COLOUR DIFFERENCE OUTPUT AND INPUT SIGNALS (PINS 29, 30, 31 AND 32); NOTE 26 S.4.1 S.4.2 signal amplitude (R-Y) (peak-to-peak value) signal amplitude (B-Y) (peak-to-peak value) note 2 note 2 - - 1.05 1.33 - - V V
LUMINANCE INPUTS AND OUTPUTS (PINS 27 AND 28); NOTE 26 S.5.1 S.5.2 S.5.3 output signal amplitude (peak-to-peak value) top sync level output impedance top sync-white - - - 1.4 2.0 250 - - - V V
Chrominance filters CHROMINANCE TRAP CIRCUIT; NOTE 27 F.1.1 F.1.2 F.1.3 F.1.4 F.1.5 trap frequency Bandwidth at fSC = 3.58 MHz Bandwidth at fSC = 4.43 MHz colour subcarrier rejection trap frequency during SECAM reception -3 dB -3 dB at nominal peaking - - - 20 - fosc 2.8 3.4 30 4.3 - - - - - MHz MHz MHz dB MHz
CHROMINANCE BANDPASS CIRCUIT F.2.1 F.2.2 F.2.3 centre frequency (CB = 0) centre frequency (CB = 1) bandpass quality factor - - - 4.26 241 fosc 1.1xfosc 3 - - - 4.31 295 MHz kHz MHz MHz
CLOCHE FILTER F.3.1 F.3.2 centre frequency Bandwidth 4.29 268
December 16, 1997
33
Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
NUMBER PARAMETER CONDITIONS
TDA884X/5X-N2 series
MIN.
TYP.
MAX.
UNIT
LUMINANCE PROCESSING Y DELAY LINE F.4.1 F.4.2 F.4.3 delay time tuning range delay time bandwidth of internal delay line note 5 8 steps note 5 - -160 8 - - positive negative Ratio negative/positive overshoot peaking control curve 63 steps - - - see Fig.9 - 15 -1 -1 6 - 27 1 3 10 480 - - 160 50 45 80 1.8 - +160 - - - - - - ns ns MHz
PEAKING CONTROL; NOTE 28 F.5.1 F.5.2 F.5.3 F.5.4 F.5.5 F.5.6 CORING STAGE F.6.1 coring range 15 IRE width of preshoot or overshoot peaking signal compression threshold overshoot at maximum peaking note 2 ns IRE % %
BLACK LEVEL STRETCHER; NOTE 29 F.7.1 F.7.2 F.7.3 F.7.4 Maximum black level shift level shift at 100% peak white level shift at 50% peak white level shift at 15% peak white 21 0 - 8 IRE IRE IRE IRE
December 16, 1997
34
Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
NUMBER PARAMETER CONDITIONS
TDA884X/5X-N2 series
MIN.
TYP.
MAX.
UNIT
Horizontal and vertical synchronization and drive circuits SYNC VIDEO INPUT (PINS 11, 13 AND 17) H.1.1 H.1.2 H.1.3 sync pulse amplitude slicing level for horizontal sync slicing level for vertical sync note 2 note 30 note 30 50 - - - - VP = 8.0 V 10%; note 5 Tamb = 0 to 70 C; note 5 - - 300 50 30 350 - - - 2 0.5 100 mV % %
HORIZONTAL OSCILLATOR H.2.1 H.2.2 H.2.3 H.2.4 free running frequency spread on free running frequency frequency variation with respect to the supply voltage frequency variation with temperature 15625 - 0.3 - Hz % % Hz
FIRST CONTROL LOOP (FILTER CONNECTED TO PIN 43); NOTE 31 H.3.1 H.3.2 H.3.3 holding range PLL catching range PLL signal-to-noise ratio of the video input signal at which the time constant is switched hysteresis at the switching point note 5 - 0.6 - 0.9 0.9 20 1.2 - - kHz kHz dB
H.3.4
- - -
3
- - -
dB s/s s
SECOND CONTROL LOOP (CAPACITOR CONNECTED TO PIN 42) H.4.1 H.4.2 control sensitivity control range from start of horizontal output to flyback at nominal shift position horizontal shift range control sensitivity for dynamic compensation Voltage to switch-on the "flash" protection Input current during protection note 32 63 steps 120 19
H.4.3 H.4.4 H.4.5 H.4.6
2 - 6 -
- 7.6 - - 0.4 - - 45 2xfH 72
- - - 1
s s/V V mA
HORIZONTAL OUTPUT (PIN 40); NOTE 33 H.5.1 H.5.2 H.5.3 H.5.4 H.5.5 H.5.6 LOW level output voltage maximum allowed output current maximum allowed output voltage duty factor frequency during switch-on and switch-off duty factor during switch-on and switch-off 35 VOUT = HIGH, note 5 IO = 10 mA - 10 - - - - tbf - VP - - - % V mA V %
December 16, 1997
Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
NUMBER
HORIZONTAL OUTPUT
TDA884X/5X-N2 series
PARAMETER (CONTINUED)
CONDITIONS - note 37 note 37 - -
MIN.
TYP. - - -
MAX.
UNIT
H.5.7 H.5.8 H.5.9
switch-on time switch-off time with RGB drive maximum switch-off time with RGB drive minimum
100 100/80 60
ms ms ms
FLYBACK PULSE INPUT AND SANDCASTLE OUTPUT (PIN 41) H.6.1 H.6.2 H.6.3 H.6.4 H.6.5 H.6.6 delay of start of burst key to start of sync required input current during flyback pulse output voltage clamped input voltage during flyback pulse width burst key pulse vertical blanking, note 34 note 2 during burst key during blanking 100 4.8 1.9 2.6 3.3 - 5.2 - 5.3 2.1 3.0 3.5 14 5.4 300 5.8 2.3 3.4 3.7 - 5.6 A V V V s lines s
VERTICAL OSCILLATOR; NOTE 35 H.7.1 H.7.2 H.7.3 H.7.4 free running frequency locking range divider value not locked locking range - 45 - 434/488 50/60 - 625/525 - - 64.5/72 - 722 Hz Hz lines lines/ frame
VERTICAL RAMP GENERATOR (PIN 51 AND 52) H.8.1 H.8.2 H.8.3 H.8.4 H.8.5 H.8.6 sawtooth amplitude (peak-to-peak value) discharge current charge current set by external resistor vertical slope charge current increase LOW level of ramp note 36 control range (63 steps) f = 60 Hz VS = 1FH; C = 100 nF; R = 39 k - - - -20 - - VA = 1FH - - 0 3.0 0.9 16 - 19 2.3 - - - +20 - - - - 4.0 V mA A % % V
VERTICAL DRIVE OUTPUTS (PINS 46 AND 47) H.9.1 H.9.2 H.9.3 differential output current (peak-to-peak value) common mode current output voltage range 0.95 400 - - - 6.3 mA A V
EHT TRACKING/OVERVOLTAGE PROTECTION (PIN 50) H.10.1 H.10.2 H.10.3 input voltage scan modulation range vertical sensitivity 1.2 -5 - 36 2.8 +5 - V % %/V
December 16, 1997
Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
NUMBER PARAMETER CONDITIONS
TDA884X/5X-N2 series
MIN. - +100 - -
TYP. -6.3 - 3.9 -
MAX.
UNIT
EHT TRACKING/OVERVOLTAGE PROTECTION (CONTINUED) H.10.4 H.10.5 H.10.6 DE-INTERLACE H.11.1 first field delay 0.5H - - - - - - - - - - - - - 65 700 8.0 1200 % A V A % A % A % A % A EW sensitivity EW equivalent output current overvoltage detection level note 32 when switched-on %/V A V -100 -
EW WIDTH; NOTE 38 H.12.1 H.12.2 H.12.3 H.12.4 control range equivalent output current EW output voltage range EW output current range 63 steps 100 0 1.0 0
EW PARABOLA/WIDTH H.13.1 H.13.2 control range equivalent output current 63 steps EW = 3FH 0 0 -43 -190 -5 -100 63 steps; SC = 00H SC = 00H 80 760 22 440
EW CORNER/PARABOLA H.14.1 H.14.2 control range equivalent output current 63 steps PW = 3FH; EW = 3FH 0 0
EW TRAPEZIUM H.15.1 H.15.2 control range equivalent output current 63 steps +5 +100
VERTICAL AMPLITUDE H.16.1 H.16.2 control range equivalent differential vertical drive output current (peak-to-peak value) 120 1140
VERTICAL SHIFT H.17.1 H.17.2 control range equivalent differential vertical drive output current (peak-to-peak value) 63 steps -5 -50 - - +5 +50 % A
S-CORRECTION H.18.1 control range 63 steps 0 - - 1.05 30 %
VERTICAL ZOOM MODE (OUTPUT CURRENT VARIATION WITH RESPECT TO NOMINAL SCAN); NOTE 39 H.19.1 H.19.2 vertical expand factor output current limiting and RGB blanking 0.75 - 1.38 -
VERTICAL SCROLL H.20.1 Control range (percentage of nominal picture amplitude) -18 - 19 %
December 16, 1997
37
Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
NUMBER PARAMETER CONDITIONS
TDA884X/5X-N2 series
MIN.
TYP.
MAX.
UNIT
Colour demodulation part CHROMINANCE AMPLIFIER D.1.1 D.1.2 ACC control range change in amplitude of the output signals over the ACC range threshold colour killer ON hysteresis colour killer OFF strong signal conditions; S/N 40 dB; note 5 noisy input signals; note 5 note 40 26 - - - - 2 dB dB
D.1.3 D.1.4 D.1.5
-30 - - -
- +3 +1
- - - -
dB dB dB
ACL CIRCUIT; NOTE 41 D.2.1 chrominance burst ratio at which the ACL starts to operate 3.0
REFERENCE PART
Phase-locked loop; note 42
D.3.1 D.3.2 catching range phase shift for a 400 Hz deviation of the oscillator frequency note 5 360 - 600 - - 2 Hz deg
Oscillator
D.4.1 D.4.2 D.4.3 D.4.4 HUE CONTROL D.5.1 D.5.2 D.5.3 hue control range hue variation for 10% VP hue variation with temperature 63 steps; see Fig.10 note 5 Tamb = 0 to 70 C; note 5 35 - - 40 0 0 - - - deg deg deg temperature coefficient of the oscillator frequency oscillator frequency deviation with respect to the supply minimum negative resistance maximum load capacitance note 5 note 5; VP = 8 V 10% - - - - - - - - 1 25 1.0 15 Hz/K Hz k pF
DEMODULATORS (PINS 29 AND 30)
General
D.6.1 D.6.2 D.6.3 D.6.4 D.6.5 (R-Y) output signal amplitude (peak-to-peak value) (B-Y) output signal amplitude (peak-to-peak value) spread of signal amplitude ratio between standards output impedance (R-Y)/(B-Y) output bandwidth of demodulators note 43 note 43 note 5 note 5 -3 dB; note 44 38 - - -1.5 - - 1.05 1.33 - 500 650 - - +1.5 - - V V dB kHz
December 16, 1997
Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
NUMBER PARAMETER CONDITIONS
TDA884X/5X-N2 series
MIN.
TYP.
MAX.
UNIT
PAL/NTSC demodulator
D.6.6 gain between both demodulators G(B-Y) and G(R-Y) residual carrier output (peak-to-peak value); only valid for PAL and NTSC signals f = fosc; (R-Y) output f = fosc; (B-Y) output f = 2fosc; (R-Y) output f = 2fosc; (B-Y) output H/2 ripple at (R-Y) output (peak-to-peak value) change of output signal amplitude with temperature change of output signal amplitude with supply voltage phase error in the demodulated signals note 5 note 5 note 5 1.60 1.78 1.96
D.6.7 D.6.8 D.6.9 D.6.10 D.6.11 D.6.12 D.6.13 D.6.14
- - - - - - - -
- - - - - 0.1 - -
10 10 10 10 25 - 0.2 8
mV mV mV mV mV %/K dB deg
SECAM demodulator
D.7.1 D.7.2 D.7.3 D.7.4 D.7.5 black level off-set pole frequency of deemphasis ratio pole and zero frequency non linearity calibration voltage pin 16 - 77 - - 3 - 85 3 - 4 7 93 - 3 5 % V kHz kHz
Base-band delay line
D.8.1 variation of output signal for adjacent time samples at constant input signals residual clock signal (peak-to-peak value) delay of delayed signal delay of non-delayed signal difference in output amplitude with delay on or off -0.1 - 0.1 dB
D.8.2 D.8.3 D.8.4 D.8.5
- 63.94 40 -
- 64.0 60 -
5 64.06 80 5
mV s ns %
December 16, 1997
39
Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
NUMBER PARAMETER CONDITIONS
TDA884X/5X-N2 series
MIN.
TYP.
MAX.
UNIT
COLOUR DIFFERENCE MATRICES (IN CONTROL CIRCUIT)
TDA 8840/41/42/43/44/54: PAL/SECAM mode; (R-Y) and (B-Y) not affected
D.9.1 D.9.2 ratio of demodulated signals ratio of demodulated signals - - -0.51 10% -0.19 25% 2.03UR -0.14UR + 1.58VR -0.31UR - 0.53VR - -
TDA 8840/41/42/43/44/54: NTSC mode; the matrix results in the following signals (nominal hue setting)
D.9.3 D.9.4 D.9.5 (B-Y) signal: 2.03/0 (R-Y) signal: 1.59/95 (G-Y) signal: 0.61/240
TDA 8846/46A/47/57; the matrix results in the following signals (nominal hue setting)
MAT-bit = 0 D.9.6 D.9.7 D.9.8 MAT-bit = 1 D.9.9 D.9.10 D.9.11 (B-Y) signal: 2.20/-1 (R-Y) signal: 1.53/99 (G-Y) signal: 0.70/223 2.20UR - 0.04VR -0.24UR + 1.51VR -0.51UR - 0.48VR 3.58/4.43 0.2 4.0 - 0.25 4.2 0.1 0.3 5.0 1.4 MHz V V V (B-Y) signal: 2.03/0 (R-Y) signal: 1.59/95 (G-Y) signal: 0.61/240 2.03UR -0.14UR + 1.58VR -0.31UR - 0.53VR
REFERENCE SIGNAL OUTPUT PIN 33; NOTE 45 D.10.1 D.10.2 D.10.3 D.10.4 reference frequency output signal amplitude (peak-to-peak value) output level to enable the comb filter output level to disable the comb filter
DYNAMIC SKIN TONE (FLESH) CONTROL; NOTE 46 D.11.1 D.11.2 D.11.3 control angle control angle correction range (angle) DSA=0 DSA=1 - - - 123 117 45 - - - deg deg deg
December 16, 1997
40
Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
NUMBER Control part SATURATION CONTROL; NOTE 25 C.1.1 saturation control range 63 steps; see Fig.11 PARAMETER CONDITIONS
TDA884X/5X-N2 series
MIN.
TYP.
MAX.
UNIT
52 - -
- 18 -
- - 0.5
dB
CONTRAST CONTROL; NOTE 25 C.2.1 C.2.2 contrast control range 63 steps dB dB tracking between the three see Fig.12 channels over a control range of 10 dB
BRIGHTNESS CONTROL C.3.1 brightness control range 63 steps; see Fig.13 - tbf 0.7 2.0 - tbf V
RGB AMPLIFIERS (PINS 19, 20 AND 21) C.4.1 output signal amplitude (peak-to-peak value) maximum signal amplitude (black-to-white) at nominal luminance input signal, nominal contrast and white-point adjustment; note 47 V
C.4.2 C.4.3
- -
tbf tbf
- -
V V
input signal amplitude (Y-input, note 47 pin 27) at which the soft clipping is activated output signal amplitude for the `red' channel (peak-to-peak value) nominal black level voltage black level voltage
C.4.4
at nominal settings for tbf contrast and saturation control and no luminance signal to the input (R-Y, PAL) - when black level stabilisation - is switched-off (via AKB bit) 1.8 14.4 - difference with black level, note 47 - - - - note 47 -
2.1
tbf
V
C.4.5 C.4.6 C.4.61 C.4.7 C.4.8 C.4.9 C.4.10 C.4.11 C.4.12 C.4.13
2.4 2.5 2.5 14.7 1 -0.5 -0.1 0.25 0.38 3
- - 3.2 15.0 - - - - - -
V V V s V V V V V dB
black level voltage control range VSD bit active; note 48 width of video blanking with HBL note 49 bit active control range of the black-current stabilisation blanking level level during leakage measurement level during "low" measuring pulse level during "high" measuring pulse adjustment range of the ratio between the amplitudes of the RGB drive voltage and the measuring pulses variation of black level with temperature
C.4.14
note 5
-
1.0
-
mV/K
December 16, 1997
41
Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
NUMBER
RGB AMPLIFIERS
TDA884X/5X-N2 series
PARAMETER (CONTINUED) note 5
CONDITIONS
MIN.
TYP.
MAX.
UNIT
C.4.15
relative variation in black level between the three channels during variations of supply voltage (10%) saturation (50 dB) contrast (20 dB) brightness (0.5 V) temperature (range 40 C) signal-to-noise ratio of the output signals residual voltage at the RGB outputs (peak-to-peak value) bandwidth of output signals
C.4.16 C.4.17 C.4.18 C.4.19 C.4.20 C.4.21 C.4.22 C.4.23 C.4.24 C.4.25 C.4.26 C.4.27 C.4.28
nominal controls nominal contrast nominal saturation nominal controls RGB input; note 50 CVBS input; note 50 at fosc at 2fosc plus higher harmonics RGB input; at -3 dB CVBS input; at -3 dB; fosc = 3.58 MHz CVBS input; at -3 dB; fosc = 4.43 MHz S-VHS input; at -3 dB
- - - - - 60 50 - - 9 - - 6 - - -
- - - - - - - - - - 2.8 3.5 - 20H 3 6
tbf tbf tbf tbf tbf - - 15 15 - - - - - - -
mV mV mV mV mV dB dB mV mV MHz MHz MHz MHz
WHITE-POINT ADJUSTMENT C.5.1 C.5.2 C.5.3 I2C-bus setting for nominal gain adjustment range of RGB drive levels gain control range to compensate spreads in picture tube characteristics HEX code dB dB
2-POINT BLACK-CURRENT STABILISATION (PIN 18); NOTE 51 C.6.1 C.6.2 C.6.3 C.6.4 C.6.5 amplitude of "low" reference current amplitude of "high" reference current acceptable leakage current maximum current during scan input impedance - - - - - - - - 8 20 100 tbf tbf - - - - - - - - A A A mA V V V
BEAM CURRENT LIMITING (PIN 22); NOTE 52 C.7.1 C.7.2 C.7.3 contrast reduction starting voltage voltage difference for full contrast reduction brightness reduction starting voltage 3.0 1.8 1.9
December 16, 1997
42
Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
NUMBER
BEAM CURRENT LIMITING
TDA884X/5X-N2 series
PARAMETER (CONTINUED)
CONDITIONS - - - - - - - -
MIN.
TYP. - - - - - - - -
MAX.
UNIT
C.7.4 C.7.5 C.7.6 C.7.7 C.7.8
voltage difference for full brightness reduction internal bias voltage detection level vertical guard minimum input current to activate the guard circuit maximum allowable current 53
1 3.3 3.65 100 1
V V V A mA
BLUE STRETCH; NOTE
C.8.1 C.8.2 C.8.3
decrease of small signal gain for BLS = 1 the red and green channel decrease of small signal gain for EBS = 1 the red channel decrease of small signal gain for EBS = 1 the green channel
14 22 8
% % %
I2C-BUS CONTROL INPUT/OUTPUT (SDA/SCL) B.1.1 B.1.2 B.1.3 B.1.4 B.1.5 B.1.6 Notes 1. On set AGC. 2. This parameter is not tested during production and is just given as application information for the designer of the television receiver. 3. Loop bandwidth BL = 60 kHz (natural frequency fN = 15 kHz; damping factor d = 2; calculated with top sync level as FPLL input signal level). 4. The IF-PLL demodulator uses an internal VCO (no external LC-circuit required) which is calibrated by means of a digital control circuit which uses the X-tal frequency of the colour decoder as a reference. The required IF frequency for the various standards is set via the I2C-bus (IFA-IFC bits in sub-address 15H). When the system is locked the resulting IF frequency is very accurate with a deviation from the nominal value of less than 25 kHz. 5. This parameter is not tested during production but is guaranteed by the design and qualified by means of matrix batches which are made in the pilot production period. 6. Measured at 10 mV (RMS) top sync input signal. 7. So called projected zero point, i.e. with switched demodulator. 8. Measured in accordance with the test line given in Fig.14. For the differential phase test the peak white setting is reduced to 87%. The differential gain is expressed as a percentage of the difference in peak amplitudes between the largest and smallest value relative to the subcarrier amplitude at blanking level. The phase difference is defined as the difference in degrees between the largest and smallest phase angle. input voltage level low-level input voltage high-level input voltage low-level input current high-level input current low-level output voltage Vi = 0 V Vi = 5.5 V SDA, IL = 3 mA 0 - 3.5 - - - - - - - - - 5.5 1.5 - -10 10 0.4 V V V A A V
December 16, 1997
43
Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
TDA884X/5X-N2 series
9. This figure is valid for the complete video signal amplitude (peak white-to-black), see Fig.15. 10. The noise inverter is only active in the "strong signal mode" (no noise detected in the incoming signal) 11. The test set-up and input conditions are given in Fig.16. The figures are measured with an input signal of 10 mV RMS. The indicated parameter values are obtained when a capacitor with a value of 1 nF is connected in parallel with the PLL loop filter on pin 5. 12. Measured at an input signal of 10 mVRMS. The S/N is the ratio of black-to-white amplitude to the black level noise voltage (RMS value). B = 5 MHz. Weighted in accordance with CCIR 567. 13. The AGC response time is also dependent on the acquisition time of the PLL demodulator. The values given are valid when the PLL is in lock. 14. The AFC control voltage is generated by the digital tuning system of the PLL demodulator. This system uses the X-tal frequency of the colour decoder as a reference and is therefore very accurate. For this reason no maximum and minimum values are given for the window sensitivity figures (parameters M.7.2 and M.7.3). The tuning information is supplied to the tuning system via the I2C-bus. 2 bits are reserved for this function. The AFC value is valid only when the SL-bit is 1. 15. The ratio of the output signal amplitudes of the deemphasis pin (pin 55) and the audio output (pin 15) is dependent on the type and/or the frequency of the X-tals connected to the IC (indicated via the XA/XB bits). The indicated values are valid for the PAL, PAL/NTSC and multi-standard versions when a 4.43 MHz X-tal is connected to pin 35 (pin 51 in the QFP-64 envelope). For the NTSC types and the other IC's (when only 3.5 MHz X-tals are used) the gain between the deemphasis output and the audio output is a factor 2 higher so that the audio output signal is not effected by the lower frequency deviation of the M/N standard. The test conditions are: Vi = 100 mVRMS, FM: 1 kHz, f = 25/50 kHz. 16. Vi = 50 mVRMS, f = 4.5/5.5 MHz; FM: 70 Hz, +/- 50 kHz deviation; AM: 1.0 kHz, 30% modulation. 17. Vi = 100 mVRMS, f = 5.5 MHz; FM: 1 kHz, +/- 17.5 kHz deviation. Measured with a bandwidth of 15 kHz and the audio attenuator at -6 dB. 18. Vi = 100 mVRMS, f = 4.5 MHz, FM: 1 kHz, +/- 100 kHz deviation. 19. Unweighted RMS value, Vi = 100 mVRMS, FM: 1 kHz, +/- 50 kHz deviation, audio attenuator at -6 dB. 20. Audio attenuator at -20 dB; temperature range 10 to 50 C. 21. The Automatic Volume Levelling (AVL) circuit stabilises automatically the audio output signal to a certain level which can be set by means of the volume control. This AVL function prevents big audio output fluctuations due to variation of the modulation depth of the transmitter. The AVL can be switched on and off via the I2C-bus. For the TDA 8846/46A the AVL is active over an input voltage range (measured at the deemphasis output) between 75 and 750 mVRMS. For the TDA 8840/41/42 this input level is dependent on the X-tals which are connected to the colour decoder. When only 3.5 MHz X-tals are connected (indicated via the XA/XB bits) the active input level is identical to that of the TDA 8846/46A. When a 4.4 MHz X-tal is connected the input range is increased to 150 to 1500 mVRMS, this to cope with the larger FM swing of European transmitters. The AVL control curve for the 2 standards is given in Fig.17 and Fig.18. The control range of +6 dB to -14 dB is valid for input signals with 50% of the maximum frequency deviation. 22. Signal with negative-going sync. Amplitude includes sync pulse amplitude. 23. This parameter is measured at nominal settings of the various controls. 24. Indicated is a signal for a colour bar with 75% saturation (chroma : burst ratio = 2.2 : 1). 25. The saturation control is active on the internal signal (YUV) and on the second RGB input. The contrast control is active on YUV and the 2 RGB inputs. Nominal contrast is specified with the DAC in position 20 HEX. Nominal saturation as maximum -10 dB.
December 16, 1997
44
Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
TDA884X/5X-N2 series
26. Several versions have a YUV interface. The luminance and colour difference out- and inputs can directly be connected. When additional picture improvement IC's (like the TDA 9170) are applied the inputs of these IC's must be ac coupled because of the black level clamp requirement. The output signal of the picture improvement IC can directly be coupled to the luminance and colour difference inputs as long as the dc level of these signals have a value between 1 and 7 Volts (for the luminance signal) or between 1 and 4 Volts (for the UV signals). When the dc level of the input signals exceed these levels the signals must be ac coupled and biased to a voltage level within these limits. To be able to apply CTI IC's like the TDA 4565/66 the gain of the luminance channel can be increased via the setting of the GAI bit in the I2C subaddress 03. 27. When the decoder is forced to a fixed subcarrier frequency (via XA/XB or the CM-bits) the chroma trap is always switched-on, also when no colour signal is identified. When 2 X-tals are active the chroma trap is switched-off when no colour signal is identified. 28. Valid for a signal amplitude on the Y-input of 0.7 V black-to-white (100 IRE) with a rise time (10% to 90%) of 70 ns and the video switch in the Y/C mode. During production the peaking function is not tested by measuring the overshoots but by measuring the frequency response of the Y output. 29. For video signals with a black level which deviates from the back-porch blanking level the signal is "stretched" to the blanking level. The amount of correction depends on the IRE value of the signal (see Fig.19). The black level is detected by means of an internal capacitor. The black level stretcher can be switched on and off via the BKS bit in the I2C-bus. The values given in the specification are valid only when the luminance input signal has an amplitude of 1 Vp-p. 30. The slicing level is independent of sync pulse amplitude. The given percentage is the distance between the slicing level and the black level (back porch). When the amplitude of the sync pulse exceeds the value of 350 mV the sync separator will slice the sync pulse at a level of 175 mV above top sync. The maximum sync pulse amplitude is 4 Vp-p. 31. To obtain a good performance for both weak signal and VCR playback the time constant of the first control loop is switched depending on the input signal condition and the condition of the I2C-bus. Therefore the circuit contains a noise detector and the time constant is switched to `slow' when too much noise is present in the signal. In the `fast' mode during the vertical retrace time the phase detector current is increased 50% so that phase errors due to head-switching of the VCR are corrected as soon as possible. Switching between the two modes can be automatically or overruled by the I2C-bus. The circuit contains a video identification circuit which is independent of first loop. This identification circuit can be used to close or open the first control loop when a video signal is present or not present on the input. This enables a stable On Screen Display (OSD) when just noise is present at the input. The coupling of the video identification circuit with the first loop can be defeated via the I2C-bus. To prevent that the horizontal synchronisation is disturbed by anti copy signals like Macrovision the phase detector is gated during the vertical retrace period so that pulses during scan have no effect on the output voltage. The width of the gate pulse is about 22 s. During weak signal conditions (noise detector active) the gating is active during the complete scan period and the width of the gate pulse is reduced to 5.7 s so that the effect of noise is reduced to a minimum. The output current of the phase detector in the various conditions are shown in Table 75. 32. The IC's have 2 protection inputs. The protection on pin 42 is intended to be used as "flash" protection. When this protection is activated the horizontal drive is switched-off immediately and then switched-on again via the slow start procedure. The protection on pin 50 is intended for overvoltage (X-ray) protection. When this protection is activated the horizontal drive can directly be switched-off (via the slow stop procedure). It is also possible to continue the horizontal drive and to set the protection bit (XPR) in the output bytes of the I2C-bus. The choice between the 2 modes of operation is made via the PRD bit.
December 16, 1997
45
Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
TDA884X/5X-N2 series
33. During switch-on the horizontal output starts with the double frequency and with a duty cycle of 75% (VOUT = high). After about 50 ms the frequency is changed to the normal value. Because of the high frequency the peak currents in the horizontal output transistor are limited. Also during switch-off the frequency is switched to the double value and the RGB drive is set to maximum so that the EHT capacitor is discharged. The switching to maximum drive occurs only when RBL=0, for RBL=1 the drive voltage remains minimum during switch-off. After about 100 ms the RGB drive is set to minimum and 50 ms later the horizontal drive is switched-off. It is possible to discharge the EHT capacitor in the vertical overscan so that the screen stays black during switch-off. This feature is activated by the OSO bit. In this condition the vertical scan is stopped and the current is set to the maximum scan value. It should be checked with the picture tube supplier whether this mode of switch-off is allowed for the given picture tube. The horizontal output is gated with the flyback pulse so that the horizontal output transistor cannot be switched-on during the flyback time. 34. The vertical blanking pulse in the RGB outputs has a width of 26 or 21 lines (50 or 60 Hz system). The vertical pulse in the sandcastle pulse has a width of 14 lines. This to prevent a phase distortion on top of the picture due to a timing modulation of the incoming flyback pulse. 35. The timing pulses for the vertical ramp generator are obtained from the horizontal oscillator via a divider circuit. During TV reception this divider circuit has 3 modes of operation: a) Search mode `large window'. This mode is switched on when the circuit is not synchronized or when a non-standard signal (number of lines per frame outside the range between 311 and 314(50 Hz mode) or between 261 and 264 (60 Hz mode) is received). In the search mode the divider can be triggered between line 244 and line 361 (approximately 45 to 64.5 Hz). b) Standard mode `narrow window'. This mode is switched on when more than 15 succeeding vertical sync pulses are detected in the narrow window. When the circuit is in the standard mode and a vertical sync pulse is missing the retrace of the vertical ramp generator is started at the end of the window. Consequently, the disturbance of the picture is very small. The circuit will switch back to the search window when, for 6 successive vertical periods, no sync pulses are found within the window. c) Standard TV-norm (divider ratio 525 (60 Hz) or 625 (50 Hz). When the system is switched to the narrow window it is checked whether the incoming vertical sync pulses are in accordance with the TV-norm. When 15 standard TV-norm pulses are counted the divider system is switched to the standard divider ratio mode. In this mode the divider is always reset at the standard value even if the vertical sync pulse is missing. When 3 vertical sync pulses are missed the system switches back to the narrow window and when also in this window no sync pulses are found (condition 3 missing pulses) the system switches over to the search window. The vertical divider needs some waiting time during channel-switching of the tuner. When a fast reaction of the divider is required during channel-switching the system can be forced to the search window by means of the NCIN bit in subaddress 08. When RGB signals are inserted the maximum vertical frequency is increased to 72 Hz. This has the consequence that the circuit can also be synchronised by signals with a higher vertical frequency like VGA. 36. Conditions: frequency is 50 Hz; normal mode; VS = 1F. 37. During switch-off the RGB drive outputs are shortly set to maximum so that the EHT capacitor of the picture tube can be discharged. The switch-off behaviour depends on the switch-off mode. When the vertical scan is set in the overscan during switch-off the RGB outputs are first set to minimum during 20 ms, then the drive is set to maximum during 80 ms followed by a period of 60 ms with the drive on minimum. When the vertical scan is active during switch-off the RGB drive voltages are directly set to maximum when the switch-off command is given. The output remain high during a period of 100 ms followed by a period of 60 ms with the drive on minimum. 38. The output range percentages mentioned for E-W control parameters are based on the assumption that 400 A variation in E-W output current is equivalent to 20% variation in picture width. December 16, 1997 46
Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
TDA884X/5X-N2 series
39. The IC's have a zoom adjustment possibility for the horizontal and vertical deflection. For this reason an extra DAC has been added in the vertical amplitude control which controls the vertical scan amplitude between 0.75 and 1.38 of the nominal scan. At an amplitude of 1.05 of the nominal scan the output current is limited and the blanking of the RGB outputs is activated. This is illustrated in Fig.21. In addition to the variation of the vertical amplitude a vertical scroll function is introduced so that it is always possible to display the most important part of the picture. The nominal scan height must be adjusted at a position of 19 HEX of the vertical "zoom" DAC and 1F HEX of the vertical scroll DAC. 40. At a chrominance input voltage of 660 mV (p-p) (colour bar with 75% saturation i.e. burst signal amplitude 300 mV (p-p)) the dynamic range of the ACC is +6 and -20 dB. 41. The ACL function can be activated by via the ACL bit in the I2C subaddress 19. The ACL circuit reduces the gain of the chroma amplifier for input signals with a chroma-to-burst ratio which exceeds a value of 3.0. 42. All frequency variations are referenced to 3.58 or 4.43 MHz carrier frequency. All oscillator specifications are measured with the Philips crystal series 9922 520 with a series capacitance of 18 pF. The oscillator circuit is rather insensitive to the spurious responses of the X-tal. As long as the resonance resistance of the third overtone is higher than that of the fundamental frequency the oscillator will operate at the right frequency. The typical crystal parameters for the X-tals mentioned above are: a) Load resonance frequency f0 = 4.433619 or 3.579545 MHz; CL = 20 pF. b) Motional capacitance CM = 20.5 fF (4.43 MHz crystal) or 14.5 fF (3.58 MHz crystal). c) Parallel capacitance C0 = 5.0 pf for both X-tals. The minimum detuning range can only be specified if both the IC and the X-tal tolerances are known and therefore the figures regarding catching range are only valid for the specified X-tal series. In this figure tolerances of the X-tal with respect to the nominal frequency, motional capacitance and ageing have been taken into account and have been counted for by gaussic addition. Whenever different typical X-tal parameters are used the following equation might be helpful for calculating the impact on the tuning capabilities: Detuning range = CM /(1 + C0/CL)2 The resulting detuning range should be corrected for temperature shift and supply voltage deviation of both the IC and the X-tal. To guarantee a catching range of 300 Hz on 4.43 MHz the minimum motional cpacitance of the X-tal must have a value 13.2 fF or higher. For a catching range of 250 Hz with the 3.58 MHz X-tal the minimum motional cpacitance must have a value of 9 fF. The actual series capacitance in the application should be CL = 18 pF to account for parasitic capacitances on and off chip. For 3-norma applications with 2 X-tals connected to one pin the maximum parasitic capacitance of the X-tal pin should not exceed 15 pF. 43. Because the base-band delay line is integrated the demodulated colour difference signals are matrixed before they are supplied to the outputs. The colour difference out- and inputs must be dc coupled. 44. This parameter indicates the bandwidth of the complete chrominance circuit including the chrominance bandpass filter. The bandwidth of the low-pass filter of the demodulator is approximately 1 MHz. 45. The subcarrier output signal can be used as reference signal for external comb filter IC's (e.g. SAA 4961). When the CMB bit is low the subcarrier signal is suppressed and the dc level is low. With the CMB bit high the output level is high and the subcarrier signal is present. 46. The Dynamic Skin Tone Correction circuit is designed such that it corrects (instantaneously and locally) the hue of those colours which are located in the area in the UV plane that matches to skin tones. The correction is dependent on the luminance, saturation and distance to the preferred axis and can be realised for 2 different angles. This angle can be set by means of the DSA bit. Because the amount of correction is dependent on the parameters of the incoming YUV signal it is not possible to give exact figures for the correction angle. The correction angle of 45 (+/-22.5) degrees is just given as an indication and is valid for an input signal with a luminance signal amplitude of 75% and a colour saturation of 50%. A graphical representation of the control behaviour is given in Fig.20. December 16, 1997 47
Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
TDA884X/5X-N2 series
47. Because of the 2-point black current stabilisation circuit both the black level and the amplitude of the RGB output signals depend on the drive characteristic of the picture tube. The system checks whether the returning measuring currents meet the requirement and adapts the output level and gain of the circuit when necessary. Therefore the typical value of the black level and amplitude at the output are just given as an indication for the design of the RGB output stage. The 2-point black level system adapts the drive voltage for each cathode in such a way that the 2 measuring currents have the right value. This has the consequence that a change in the gain of the output stage will be compensated by a gain change of the RGB control circuit. Because different picture tubes may require different drive voltage amplitudes the ratio between the output signal amplitude and the inserted measuring pulses can be adapted via the I2C-bus. This is indicated in the parameter "Adjustment range of the ratio between the amplitudes of the RGB drive voltage and the measuring pulses". Because of the dependence of the output signal amplitude on the application the soft clipping limiting has been related to the input signal amplitude. 48. For the alignment of the picture tube the vertical scan can be stopped by means of the VSD bit. In that condition a certain black level is inserted at the RGB outputs. The value of this level can be adjusted by means of the brightness control DAC. 49. When the reproduction of 4:3 pictures on a 16:9 picture tube is realised by means of a reduction of the horizontal scan amplitude the edges of the picture may slightly be disturbed. This effect can be prevented by adding an additional blanking to the RGB signals. The blanking pulse is derived form the horizontal oscillator and is directly related to the incoming video signal (independent of the flyback pulse). The additional blanking overlaps the normal blanking signal with about 1 s on both sides. This blanking is activated with the HBL bit (only in the TDA8843/44/47/54/57). 50. Signal-to-noise ratio (S/N) is specified as peak-to-peak signal with respect to RMS noise (bandwidth 5 MHz). 51. This is a current input. 52. The beam current limiting and the vertical guard function have been combined on this pin. The beam current limiting function is active during the vertical scan period. 53. Via the "blue stretch" (BLS bit) or "extended blue stretch" (EBS bit) function the colour temperature of the bright scenes (amplitudes which exceed a value of 80% of the nominal amplitude) can be increased. This effect is obtained by decreasing the small signal gain of the red and green channel signals which exceed the 80% level. The effect is illustrated in Fig.22.
December 16, 1997
48
Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
Table 75 Output current of the phase detector in the various conditions I2C-BUS COMMANDS VID - - - - - - - - 0 - Note POC 0 0 0 0 0 0 0 - 0 1 FOA 0 0 0 0 0 1 1 1 - - FOB 0 0 0 1 1 0 0 1 - - IC CONDITIONS IDENT yes yes yes yes yes yes yes - no - COIN yes yes no yes no yes yes - - - NOISE no yes - - - no yes - - -
TDA884X/5X-N2 series
-1 CURRENT/MODE SCAN 180 30 180 30 180 180 30 180 6 - V-RETR 270 30 270 30 270 270 30 270 6 - GATING yes 1) yes no yes no yes yes no no - MODE auto auto auto slow slow fast slow fast OSD off
1. Only during vertical retrace, width 22 s. In the other conditions the width is 5.7 s and the gating is continuous.
December 16, 1997
49
Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
TDA884X/5X-N2 series
0 dB -20
% 80
-40
60
-60
40
-80
20
0
10
20
30
0 40 DAC (HEX)
10
20
30
40 DAC (HEX)
Overshoot in direction `black'.
Fig.8 Volume control curve
Fig.9 Peaking control curve.
MLA739 - 1
MLA740 - 1
50 (deg) 30
300 250
(%)
% 225 250
200 175 150 125 150
10
200
10
100
100
30
75 50
50
50 0 10 20 30 40 DAC (HEX)
25
00
0
10
20
30 40 DAC (HEX)
Fig.10 Hue control curve.
Fig.11 Saturation control curve.
December 16, 1997
50
Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
TDA884X/5X-N2 series
MLA741 - 1 MLA742 - 1
100 (%) 90 80
0.7 (V) 0.35
70 60 50 40 30 20 10 0 10 20 30 40 DAC (HEX) 0.7 0 0 10 20 30 40 DAC (HEX) 0.35 0
Fig.12 Contrast control curve.
Fig.13 Brightness control curve.
MBC211
MBC212
100% 16 % 100% 92% 86% 72% 58% 44% 30% 30% 10 12 for negative modulation 100% = 10% rest carrier 22 26 32 36 40 44 48 52 56 60 64 s
Fig.14 Video output signal.
Fig.15 Test signal waveform.
December 16, 1997
51
Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
TDA884X/5X-N2 series
3.2 dB 10 dB 13.2 dB 30 dB 13.2 dB 30 dB
SC CC BLUE
PC
SC CC YELLOW
PC
MBC213
PC
SC
ATTENUATOR
TEST CIRCUIT
SPECTRUM ANALYZER
CC
gain setting adjusted for blue
MBC210
Input signal conditions: SC = sound carrier; CC = colour carrier; PC = picture carrier. All amplitudes with respect to top sync level. V O at 3.58 or 4.4 MHz Value at 0.92 or 1.1 MHz = 20 log ----------------------------------------------------------- + 3.6 dB V O at 0.92 or 1.1 MHz V O at 3.58 or 4.4 MHz Value at 2.66 or 3.3 MHz = 20 log ----------------------------------------------------------V O at 2.66 or 3.3 MHz
Fig.16 Test set-up intermodulation.
December 16, 1997
52
Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
TDA884X/5X-N2 series
CHARACTERISTIC POINTS AVL Deemphasis voltage FM swing 75 7.5
A 150 15
B 250 25
C 750 75
D
UNIT mVRMS kHz
1.8
1.0
AVL is OFF
AVL is ON
100.0m 10.0m
A
100.0m
B
C
D
1.0 2.0 DEEMP
Fig.17 AVL characteristic for TDA 8840/41/42/46/46A for 3.5 MHz standard
December 16, 1997
53
Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
TDA884X/5X-N2 series
CHARACTERISTIC POINTS AVL Deemphasis voltage FM swing 150 15
A 300 30
B 500 50
C 150
D 1500
UNIT mVRMS kHz
1.8
1.0
AVL is OFF
AVL is ON
100.0m 10.0m 100.0m
A
B
C
1.0
D
2.0 DEEMP
Fig.18 AVL characteristic for TDA 8840/41/42/46/46A for 4.4 MHz standard
December 16, 1997
54
Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
TDA884X/5X-N2 series
OUTPUT (IRE) 100
80
60
40
20 B INPUT (IRE) 20 40 60 80 100
0 A
B
-20
A
A-A: MAXIMUM BLACK LEVEL SHIFT
B-B: LEVEL SHIFT AT 15% OF PEAK WHITE
Fig.19 I/O relation of the black level stretch circuit
December 16, 1997
55
Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
TDA884X/5X-N2 series
red
V
I-axis
fully saturated colours
yellow
U
Fig.20 Skin tone correction range for a correction angle of 123 deg.
December 16, 1997
56
Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
TDA884X/5X-N2 series
TOP PICTURE % 60 50 VERTICAL POSITION 138% 40 30 75% 20 10 0 -10 -20 -30 -40 -50 -60 T/2 TIME T 100%
BOTTOM PICTURE
BLANKING FOR EXPANSION OF 138%
Fig.21 Sawtooth waveform and blanking pulse of the TDA 884X/5X
December 16, 1997
57
Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
TDA884X/5X-N2 series
Output (%)
100
BLUE GREEN (EBS=1) RED/GREEN (BLS=1)
95
RED (EBS=1)
90
85
80
85
90
95
100 Input (%)
Fig.22 Blue stretch characteristics
December 16, 1997
58
Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
TEST AND APPLICATION INFORMATION
TDA884X/5X-N2 series
BAND IF VIDEO OUT AUDIO OUT PASS AUDIO IN SCL SDA R2 B2 G2 BL2 R1 B1 G1 BL1
FROM TUNER
SAW
6 48 49
1
2
15
7
8
23 24 25 26 21 20 19
R G B
FILTER
18
CVBS INT TRAP
BLACK CURRENT BEAM CURRENT
13
TDA 884X/5X
22
45
CVBS-EXT CVBS/Y Chr.
E-W OUT V-DR A V-DR B H-OUT
17 11
46 47 40
10 38
35
34
29 30 28
Y
27 32 31
41
4.43 CVBS-1 CVBS-2
3.58
R-Y B-Y
R2 G2
BL2
B2
Fig.23 Application diagram.
December 16, 1997
59
Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
East-West output stage In order to obtain correct tracking of the vertical and horizontal EHT-correction, the EW output stage should be dimensioned as illustrated in Fig.24. Resistor REW determines the gain of the EW output stage. Resistor Rc determines the reference current for both the vertical sawtooth generator and the geometry processor. The preferred value of Rc is 39 k which results in a reference current of 100 A (Vref = 3.9 V).
TDA884X/5X-N2 series
The value of REW must be: V scan R EW = R c x ---------------------18 x V ref Example: With Vref = 3.9 V; Rc = 39 k and Vscan = 120 V then REW = 68 k.
handbook, full pagewidth
VDD
HORIZONTAL DEFLECTION STAGE R ew
V scan
TDA 884X TDA8366
43 45 EWD EW output stage DIODE MODULATOR V EW
52 50
Rc 39 k (2%) I ref V ref
49 51 C saw 100 nF (5%)
MLA744 - 1
Fig.24 East-West output stage.
December 16, 1997
60
Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
TDA884X/5X-N2 series
700 IVERT 500 (A) 300 100 -100 -300 -500 -700 0 T/2 TIME T
VA = 0, 31H and 63H; VSH = 31H; SC = 0.
VS = 0, 31H and 63H; VA = 31H; VHS = 31H; SC = 0.
Fig.25 Control range of vertical amplitude.
Fig.26 Control range of vertical slope.
VSH = 0, 31H and 63H; VA = 31H; SC = 0.
SC = 0, 31H and 63H; VA = 31H; VHS = 31H.
Fig.27 Control range of vertical shift.
Fig.28 Control range of S-correction.
December 16, 1997
61
Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
TDA884X/5X-N2 series
IEW IEW (A) 1200 1000 800 600 400 200 0 0 T/2 TIME T 0 T/2 TIME T (A) 900 800 700 600 500 400 300
PW = 0, 31H and 63H; EW = 31H; CP = 31H. EW = 0, 31H and 63H; PW = 31H; CP = 31H.
Fig.29 Control range of EW width.
Fig.30 Control range of EW parabola/width ratio.
IEW (A) 900 800 700 600 500 400 300 0 T/2 TIME T
IEW (A) 900 800 700 600 500 400 300 0 T/2 TIME T
CP = 0, 31H and 63H; EW = 31H; PW = 63H.
TC = 0, 31H and 63H; EW = 31H; PW = 31H.
Fig.31 Control range of EW corner/parabola ratio.
Fig.32 Control range of EW trapezium correction.
December 16, 1997
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Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
Adjustment of geometry control parameters The deflection processor of the TDA8840/41/42/46/46A offers 5 control parameters for picture alignment, viz: * S-correction * vertical amplitude * vertical slope * vertical shift * horizontal shift. The TDA 8843/44/47/54H/57H offer in addition: * EW width * EW parabola width * EW corner parabola * EW trapezium correction. * vertical zoom * vertical scroll It is important to notice that the IC's are designed for use with a DC-coupled vertical deflection stage. This is the reason why a vertical linearity alignment is not necessary (and therefore not available). For a particular combination of picture tube type, vertical output stage and EW output stage it is determined which are the required values for the settings of S-correction, EW parabola/width ratio and EW corner/parabola ratio. These parameters can be preset via the I2C-bus, and do not need any additional adjustment. The rest of the parameters are preset with the mid-value of their control range (i.e. 1FH), or with the values obtained by previous TV-set adjustments. The vertical shift control is meant for compensation of off-sets in the external vertical output stage or in the picture tube. It can be shown that without compensation these off-sets will result in a certain linearity error, especially with picture tubes that need large S-correction. The total linearity error is in first order approximation proportional to the value of the off-set, and to the square of the S-correction needed. The necessity to use the vertical shift alignment depends on the expected off-sets in vertical output stage and picture tube, on the required value of the S-correction, and on the demands upon vertical linearity.
TDA884X/5X-N2 series
For adjustment of the vertical shift and vertical slope independent of each other, a special service blanking mode can be entered by setting the SBL bit HIGH. In this mode the RGB-outputs are blanked during the second half of the picture. There are 2 different methods for alignment of the picture in vertical direction. Both methods make use of the service blanking mode. The first method is recommended for picture tubes that have a marking for the middle of the screen. With the vertical shift control the last line of the visible picture is positioned exactly in the middle of the screen. After this adjustment the vertical shift should not be changed. The top of the picture is placed by adjustment of the vertical amplitude, and the bottom by adjustment of the vertical slope. The second method is recommended for picture tubes that have no marking for the middle of the screen. For this method a video signal is required in which the middle of the picture is indicated (e.g. the white line in the circle test pattern). With the vertical slope control the beginning of the blanking is positioned exactly on the middle of the picture. Then the top and bottom of the picture are placed symmetrical with respect to the middle of the screen by adjustment of the vertical amplitude and vertical shift. After this adjustment the vertical shift has the right setting and should not be changed. If the vertical shift alignment is not required VSH should be set to its mid-value (i.e. VSH = 1F). Then the top of the picture is placed by adjustment of the vertical amplitude and the bottom by adjustment of the vertical slope. After the vertical picture alignment the picture is positioned in the horizontal direction by adjustment of the EW width and the horizontal shift. Finally (if necessary) the left- and right-hand sides of the picture are aligned in parallel by adjusting the EW trapezium control. To obtain the full range of the vertical zoom function with the TDA 8844/47/54H/57H the adjustment of the vertical geometry should be carried out at a nominal setting of the zoom DAC at position 19 HEX and the vertical scroll DAC at position 1F HEX.
December 16, 1997
63
Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
PACKAGE OUTLINES
SDIP56: plastic shrink dual in-line package; 56 leads (600 mil)
TDA884X/5X-N2 series
SOT400-1
seating plane
D
ME
A2 A
L
A1 c Z e b1 wM (e 1) MH b 56 29
pin 1 index E
1
28
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 5.08 A1 min. 0.51 A2 max. 4.0 b 1.3 0.8 b1 0.53 0.40 c 0.32 0.23 D (1) 52.4 51.6 E (1) 14.0 13.6 e 1.778 e1 15.24 L 3.2 2.8 ME 15.80 15.24 MH 17.15 15.90 w 0.18 Z (1) max. 2.3
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT400-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-12-06
Fig.33 Plastic shrink dual in-line package; 56 leads (600 mil) SDIP56; SOT400AA1.
December 16, 1997
64
Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
TDA884X/5X-N2 series
handbook, full pagewidth
seating plane
0.10 S 18.2 17.6
S
B 52 51
64 1 pin 1 index
1.2 (4x) 0.8 1.0
0.20 M B 0.50 0.35 19 20 0.50 0.35 14.1 13.9 32 1.2 (4x) 0.8 33 0.20 M A
20.1 24.2 19.9 23.6
1.0
X
A
2.90 2.65
1.4 1.2 0.25 0.05 0.25 0.14 3.2 2.7
1.0 0.6 detail X
0 to 7 o
MSA327
Dimensions in mm.
Fig.34 Plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm. December 16, 1997 65
Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
SOLDERING Plastic dual in-line packages BY DIP OR WAVE The maximum permissible temperature of the solder is 260 C; this temperature must not be in contact with the joint for more than 5 s. The total contact time of successive solder waves must not exceed 5 s. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified storage maximum. If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron below the seating plane (or not more than 2 mm above it). If its temperature is below 300 C, it must not be in contact for more than 10 s; if between 300 and 400 C, for not more than 5 s. Plastic quad flat-packs BY WAVE During placement and before soldering, the component must be fixed with a droplet of adhesive. After curing the adhesive, the component can be soldered. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder bath is 10 s, if allowed to cool to less than 150 C within 6 s. Typical dwell time is 4 s at 250 C.
TDA884X/5X-N2 series
A modified wave soldering technique is recommended using two solder waves (dual-wave), in which a turbulent wave with high upward pressure is followed by a smooth laminar wave. Using a mildly-activated flux eliminates the need for removal of corrosive residues in most applications. BY SOLDER PASTE REFLOW Reflow soldering requires the solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the substrate by screen printing, stencilling or pressure-syringe dispensing before device placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt, infrared, and vapour-phase reflow. Dwell times vary between 50 and 300 s according to method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 min at 45 C. REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING
IRON OR PULSE-HEATED SOLDER TOOL)
Fix the component by first soldering two, diagonally opposite, end pins. Apply the heating tool to the flat part of the pin only. Contact time must be limited to 10 s at up to 300 C. When using proper tools, all other pins can be soldered in one operation within 2 to 5 s at between 270 and 320 C. (Pulse-heated soldering is not recommended for SO packages.) For pulse-heated solder tool (resistance) soldering of VSO packages, solder is applied to the substrate by dipping or by an extra thick tin/lead plating before package placement.
December 16, 1997
66
Philips Semiconductors
Tentative Device Specification
I2C-bus controlled PAL/NTSC/SECAM TV processors
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA884X/5X-N2 series
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
December 16, 1997
67
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997
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SCA53
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